A method of manufacturing a flip-chip nitride semiconductor light emitting element includes steps of providing a nitride semiconductor light emitting element structure; forming an insulating protective layer on the nitride semiconductor light emitting element structure; forming a resist pattern having openings above an n-side electrode connecting surface and a p-side electrode connecting surface; etching the protective layer to expose the n-side electrode connecting surface and the p-side electrode connecting surface using the resist pattern as a mask; forming a first metal layer that becomes an n-side electrode and a p-side electrode, the first metal layer being formed as a continuous layer disposed on the n-side electrode connecting surface, the p-side electrode connecting surface and the resist pattern; forming a second metal layer that becomes metal bumps by electrolytic plating using the first metal layer as an electrode for the electrolytic plating; and removing the resist pattern.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of manufacturing a flip-chip nitride semiconductor light emitting element, the method comprising: a step of providing a nitride semiconductor light emitting element structure having an n-type nitride semiconductor layer and a p-type nitride semiconductor layer, which are laminated on a substrate, wherein an n-side electrode connecting surface of the n-type nitride semiconductor layer and a p-side electrode connecting surface of the p-type nitride semiconductor layer are on the same side of the substrate; a protective layer forming step of forming an insulating protective layer on the nitride semiconductor light emitting element structure; a first resist pattern forming step of forming a first resist pattern having openings above the n-side electrode connecting surface and the p-side electrode connecting surface; a protective layer etching step of etching the protective layer to expose the n-side electrode connecting surface and the p-side electrode connecting surface using the first resist pattern as a mask; a first metal layer forming step of forming a first metal layer that becomes an n-side electrode and a p-side electrode, the first metal layer being formed as a continuous layer disposed on the n-side electrode connecting surface, the p-side electrode connecting surface and the first resist pattern; a second resist pattern forming step of forming a second resist pattern having openings above the openings of the first resist pattern, a second metal layer forming step of forming a second metal layer that becomes metal bumps formed on the n-side electrode and the p-side electrode by electrolytic plating using the first metal layer as an electrode for the electrolytic plating; and a resist pattern removing step of, after the second metal layer forming step, removing the first resist pattern, the second resist pattern, and the first metal layer formed on the first resist pattern.
2. The method according to claim 1 , further comprising a second metal layer height adjusting step of adjusting a height from the upper surface of the substrate to the upper surface of the second metal layer formed on the n-side electrode so as to be same as a height from the upper surface of the substrate to the upper surface of the second metal layer formed on the p-side electrode after the second metal layer forming step.
3. The method according to claim 1 , wherein the steps are performed sequentially in the order recited in claim 1 .
4. The method according to claim 1 , wherein the protective layer is formed by sputtering.
5. The method according to claim 1 , wherein the protective layer is formed of SiO 2 .
6. The method according to claim 1 , wherein the first metal layer is a mono-layered film.
7. The method according to claim 1 , wherein the first metal layer is a multi-layered.
8. The method according to claim 1 , wherein a thickness of the second resist pattern is larger than thicknesses of the metal bumps.
9. The method according to claim 1 , wherein widths of the openings of the second resist pattern are smaller than widths of the openings of the first resist pattern.
10. The method according to claim 1 , wherein widths of the openings of the second resist patter are equal to or larger than widths of the openings of the first resist pattern.
11. The method according to claim 1 , wherein no metal layer is interposed between the n-side electrode and the metal bump formed thereon, and no metal layer is interposed between the p-side electrode and the metal bump formed thereon.
12. The method according to claim 1 , wherein the first resist pattern and the second resist pattern are removed sequentially.
13. The method according to claim 1 , wherein the first resist pattern and the second resist pattern are removed simultaneously.
14. A method of manufacturing a flip-chip nitride semiconductor light emitting element, the method comprising: a step of providing a nitride semiconductor light emitting element structure having an n-type nitride semiconductor layer and a p-type nitride semiconductor layer, which are laminated on a substrate, wherein an n-side electrode connecting surface of the n-type nitride semiconductor layer and up-side electrode connecting surface of the p-type nitride semiconductor layer are on the same side of the substrate; a protective layer forming step of forming an insulating protective layer on the nitride semiconductor light emitting element structure; a resist pattern forming step of forming a resist pattern having openings above the n-side electrode connecting surface and the p-side electrode connecting surface; a protective layer etching step of etching the protective layer to expose the n-side electrode connecting surface and the p-side electrode connecting surface using the resist pattern as a mask; a first metal layer forming step of forming a first metal layer that becomes n-side electrode and up-side electrode, the first metal layer being formed as a continuous layer disposed on the n-side electrode connecting surface, the p-side electrode connecting surface and the resist pattern; a second metal layer forming step of forming a second metal layer that becomes metal bumps by electrolytic plating using the first metal layer as an electrode for the electrolytic plating; and a resist pattern removing step of, after the second metal layer forming step, removing the resist pattern and the first metal layer formed on the resist pattern.
15. The method according to claim 14 , further comprising a second metal layer height adjusting step of adjusting a height from the upper surface of the substrate to the upper surface of the second metal layer formed on the n-side electrode so as to be same as a height from the upper surface of the substrate to the upper surface of the second metal layer formed on the p-side electrode after the second metal layer forming step.
16. The method according to claim 14 , wherein the steps are performed sequentially in the order recited in claim 14 .
17. The method according to claim 14 , wherein the protective layer is formed by sputtering.
18. The method according to claim 14 , wherein the protective layer is formed of SiO 2 .
19. The method according to claim 14 , wherein the first metal layer is a mono-layered.
20. The method according to claim 14 , wherein the first metal layer is a multi-layered.
21. The method according to claim 14 , wherein a thickness of the second resist pattern is larger than thicknesses of the metal bumps.
22. The method according to claim 14 , wherein no metal layer is interposed between the n-side electrode and the metal bump formed thereon, and no metal layer is interposed between the p-side electrode and the metal bump formed thereon.
23. The method according to claim 14 , wherein the resist pattern removing step is performed such that side surfaces of the metal bumps are coated with the first metal layer that was formed on side surfaces of the resist pattern during the first metal layer forming step.
24. A method of manufacturing a flip-chip nitride semiconductor light emitting element, the method comprising: a step of providing a nitride semiconductor light emitting element structure having an n-type nitride semiconductor layer and a p-type nitride semiconductor layer, which are laminated on a substrate, wherein an n-side electrode connecting surface of the n-type nitride semiconductor layer and a p-side electrode connecting surface of the p-type nitride semiconductor layer are on the same side of the substrate; a protective layer forming step of forming an insulating protective layer on the nitride semiconductor light emitting element structure; a first resist pattern forming step of forming a first resist pattern having openings above the n-side electrode connecting surface and the p-side electrode connecting surface; a protective layer etching step of etching the protective layer to expose the n-side electrode connecting surface and the p-side electrode connecting surface using the first resist pattern as a mask; a first metal layer forming step of forming a first metal layer that becomes an n-side electrode and a p-side electrode, the first metal layer being formed as a continuous layer disposed on the n-side electrode connecting surface, the p-side electrode connecting surface and the first resist pattern; a second resist pattern forming step of forming a second resist pattern having openings above the openings of the first resist pattern; a second metal layer forming step of forming a second metal layer that becomes metal bumps formed on the n-side electrode and the p-side electrode by electrolytic plating using the first metal layer as an electrode for the electrolytic plating; and a resist pattern removing step of removing the first resist pattern and the second resist pattern, wherein the steps are performed sequentially in the order recited.
25. The method according to claim 24 , wherein no metal layer is interposed between the n-side electrode and the metal bump formed thereon, and no metal layer is interposed between the p-side electrode and the metal bump formed thereon.
26. A method of manufacturing a flip-chip nitride semiconductor light emitting element, the method comprising: a step of providing a nitride semiconductor light emitting element structure having an n-type nitride semiconductor layer and a p-type nitride semiconductor layer, which are laminated on a substrate, wherein an n-side electrode connecting surface of the n-type nitride semiconductor layer and a p-side electrode connecting surface of the p-type nitride semiconductor layer are on the same side of the substrate; a protective layer forming step of forming an insulating protective layer on the nitride semiconductor light emitting element structure; a resist pattern forming step of forming a first resist pattern having openings above the n-side electrode connecting surface and the p-side electrode connecting surface; a protective layer etching step of etching the protective layer to expose the n-side electrode connecting surface and the p-side electrode connecting surface using the first resist pattern as a mask; a first metal layer forming step of forming a first metal layer that becomes an n-side electrode and a p-side electrode, the first metal layer being formed as a continuous layer disposed on the n-side electrode connecting surface, the p-side electrode connecting surface and the resist pattern; a second metal layer forming step of forming a second metal layer that becomes metal bumps by electrolytic plating using the first metal layer as an electrode for the electrolytic plating; and a resist pattern removing step of removing the resist pattern, wherein the steps are performed sequentially in the order recited.
27. The method according to claim 26 , wherein no metal layer is interposed between the n-side electrode and the metal bump formed thereon, and no metal layer is interposed between the p-side electrode and the metal bump formed thereon.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 26, 2012
January 5, 2016
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.