Disclosed are a resistance-variable memory device including a carbide-based solid electrolyte membrane that has stable memory at a high temperature and a manufacturing method thereof. The resistance-variable memory device includes: a lower electrode, the carbide-based solid electrolyte membrane arranged on the lower electrode, and an upper electrode arranged on the solid electrolyte membrane. In addition, the method for manufacturing the resistance-variable memory device comprises: a step for forming the lower electrode on a substrate, a step for forming the carbide-based solid electrolyte membrane on the lower electrode, and a step for forming the upper electrode on the solid electrolyte membrane.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A resistance-variable memory device comprising: a lower electrode; an insulating layer formed on the lower electrode and having a contact hole exposing the lower electrode; a carbide-based solid electrolyte membrane disposed on and contacting the lower electrode filling the contact hole, wherein the carbide-based solid electrolyte membrane is one selected from the group consisting of a Cu x C 1-x layer, an Ag x C 1-x layer, and an Au x C 1-x , and wherein the x ranges from 0.1 to 0.8; and an upper electrode disposed on and contacting the metal carbide solid electrolyte membrane.
2. The resistance-variable memory device of claim 1 , wherein the carbide-based solid electrolyte membrane is an amorphous layer.
3. The resistance-variable memory device of claim 1 , wherein the upper electrode is a Pt layer, a Ru layer, an Ir layer, an Al layer, a Ti layer, a Cu layer, or a Ni layer.
4. The resistance-variable memory device of claim 1 , wherein the lower electrode is a Pt layer, a Ru layer, an Ir layer, or an Al layer.
5. The resistance-variable memory device of claim 1 , wherein the insulating layer is a SiO2 layer.
6. A method of manufacturing a resistance-variable memory device, the method comprising: forming a lower electrode on a substrate; forming an insulating layer on the lower electrode, the insulating layer having a contact hole exposing the lower electrode; forming a carbide-based solid electrolyte membrane on the lower electrode to contact the lower electrode filling the contact hole, wherein the carbide-based solid electrolyte membrane is one selected from the group consisting of a Cu x C 1-x layer, an Ag x C 1-x layer, and an Au x C 1-x layer, and wherein the x ranges from 0.1 to 0.8; and forming an upper electrode on the metal carbide solid electrolyte membrane to contact the metal carbide solid electrolyte membrane.
7. The method of claim 6 , wherein the carbide-based solid electrolyte membrane is formed using a sputtering method.
8. The resistance-variable memory device of claim 1 , wherein the carbide-based solid electrolyte membrane is the Cu x C 1-x layer, and the content ratio of Cu to C is about 6:4.
9. The method of claim 6 , wherein the carbide-based solid electrolyte membrane is the Cu x C 1-x layer and the content ratio of Cu to C is about 6:4.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 22, 2009
January 5, 2016
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