Semiconductor device

1. A semiconductor device comprising: a compression block configured to compare and compress data of a plurality of core array blocks, by a unit of a group; a combination block configured to combine outputs of the compression block and output compression data; and a control block configured to latch the compression data and output latched data, and drive the latched data and the compression data and output resultant data to a first data line and a second data line.

2. The semiconductor device according to claim 1 , wherein a first control signal and a second control signal are controlled in their logic states by a level of a most significant column address.

3. The semiconductor device according to claim 2 , wherein the most significant column address toggles by the unit of a half tCCD (CAS to CAS delay time).

4. The semiconductor device according to claim 1 , wherein column data of different groups are sequentially activated by the level of the most significant column address, and are transferred as the compression data.

5. The semiconductor device according to claim 1 , wherein the control block comprises: a latch unit configured to latch the compression data according to a first control signal and output the latched data; a first driving unit configured to drive the compression data according to a second control signal and output resultant data to the first data line; and a second driving unit configured to drive the latched data according to the second control signal and output resultant data to the second data line.

6. The semiconductor device according to claim 5 , wherein, in the driving units, enable times of the first control signal and the second control signal are different from each other, and the compression data and the latched data are simultaneously outputted when the second control signal is enabled.

7. The semiconductor device according to claim 1 , further comprising: a test control block configured to generate a first control signal and a second control signal according to a column address, a clock and a sensing enable signal.

8. The semiconductor device according to claim 7 , wherein the test control block comprises: a write command control unit configured to generate a write command signal according to the column addresses and the clock; a read command control unit configured to generate a read command signal according to the column addresses and the clock; a column address control unit configured to control a column address according to the column addresses, the clock, the write command signal and the read command signal; and a control signal generation unit configured to control the first control signal and the second control signal according to the sensing enable signal and the column address.

9. The semiconductor device according to claim 8 , wherein the write command control unit comprises: a write command decoder configured to decode the column addresses in synchronization with the clock, and output a write signal; a plurality of shift registers configured to sequentially shift the write signal in synchronization with the clock, and output a write control signal; and a logic combing section configured to logic-combine the write signal and the write control signal, and output the write command signal.

10. The semiconductor device according to claim 8 , wherein the read command control unit comprises: a read command decoder configured to decode the column addresses in synchronization with the clock, and output a read signal; a plurality of shift registers configured to sequentially shift the read signal in synchronization with the clock, and output a read control signal; and a logic combing section configured to logic-combine the read signal and the read control signal, and output the read command signal.

11. The semiconductor device according to claim 8 , wherein the column address control unit comprises: an address latch section configured to latch the column addresses in synchronization with the clock; a counter configured to count an output address of the address latch section in synchronization with the clock; an output driving section configured to toggle an output of the counter in synchronization with a command clock, and generate the column address; and a clock generating section configured to combine the write command signal and the read command signal, and generate the command clock.

12. The semiconductor device according to claim 8 , wherein the control signal generation unit comprises: a delay section configured to delay the sensing enable signal by a predetermined time, and generate an enable signal; and a control signal output section configured to logic-combine the enable signal and the column address, and output the first control signal and the second control signal.

13. The semiconductor device according to claim 12 , wherein the control signal output section alternately activates the first control signal and the second control signal according to a level of the column address at a time when the enable signal is activated.

14. The semiconductor device according to claim 1 , wherein the compression block compares and compresses the data of the plurality of core array blocks by dividing them into 2 prefetch groups.

15. The semiconductor device according to claim 1 , further comprising: a plurality of column decoders configured to decode the column address and select corresponding cells of the plurality of core array blocks; a plurality of input/output sense amplifiers configured to sense and amplify read data applied from the plurality of core array blocks according to the sensing enable signal; a plurality of write driving units configured to drive write data applied from a global input/output line according to a write enable signal, and output resultant data to the plurality of core array blocks; a plurality of driving units configured to drive data applied from the plurality of input/output sense amplifiers, and output resultant data to the compression block.

16. A semiconductor device comprising: a compression block configured to perform a compression test for data in a probe test and output a compression data; a combination block configured to combine and output the compression data; and a control block configured to latch the compression data and output latched data, and drive the compression data and output resultant data to a first data line and a second data line.

17. The semiconductor device of claim 16 , wherein the control block comprises: a latch unit configured to latch the compression data and output the latched data; a first driving unit configured to drive the compression data and output the resultant data to the first data line; and a second driving unit configured to drive the latched data and output the resultant data to the second data line.

18. The semiconductor device of claim 17 , further comprising: a test control block configured to generate a first control signal and a second control signal and output the first control signal and the second control signal to the control block.

19. The semiconductor device of claim 18 , wherein the test control block is configured to output a write command signal and a read command signal and generate the first control signal and the second control signal according to a sensing enable signal and a column address.

20. The semiconductor device of claim 19 , further comprising: a write command control unit configured to decode the column address according to a clock, output a write signal, and shift the write signal according to the clock and output a write control signal.