In an n-channel HK/MG transistor including: a gate insulating film made of a first high dielectric film containing La and Hf; and a gate electrode which is formed of a stacked film of a metal film and a polycrystalline Si film and which is formed in an active region in a main surface of a semiconductor substrate and surrounded by an element separation portion formed of an insulating film containing oxygen atoms, a second high dielectric film which contains Hf but whose La content is smaller than a La content of the first high dielectric film is formed below the gate electrode which rides on the element separation portion, instead of the first high dielectric film.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of manufacturing a semiconductor device including a first MISFET and a second MISFET, comprising steps of: (a) forming an element separation portion in a semiconductor substrate, thereby first and second regions of the semiconductor substrate are defined; (b) forming a first gate insulating film over the first region and the element separation portion; (c) forming a second gate insulating film over the second region and the element separation portion; (d) forming a first dummy gate over the first and second gate insulating films; (e) forming an interlayer insulating film over the first and second regions in order to cover the first dummy gate; (f) after the step (e), exposing a top surface of the first dummy gate by performing a CMP method to the interlayer insulating film; (g) after the step (f), forming a first trench over the first and second gate insulating films by removing the first dummy gate; (h) embedded a first metal film in the first trench; and (i) removing the first metal film being out of the first trench, wherein the first MISFET includes the first gate insulating film and the first metal film, wherein the second MISFET includes the second gate insulating film and the first metal film, wherein the first gate insulating film is a different film from the second gate insulating film, and wherein, on the element separation portion interposed between the first region and the second region, a length of the first gate insulating film is shorter than a length of the second gate insulating film.
2. A method of manufacturing a semiconductor device according to the claim 1 , wherein the first and second MISFETs constitute a CMOS invertors.
3. A method of manufacturing a semiconductor device according to the claim 1 , wherein the first gate insulating film includes Hf, O and La, and wherein the second gate insulating film includes Hf and O and does not include La.
4. A method of manufacturing a semiconductor device according to the claim 1 , wherein the first metal film includes Al.
5. A method of manufacturing a semiconductor device including a first MISFET and a second MISFET, comprising steps of: (a) forming an element separation portion in a semiconductor substrate, thereby first and second regions of the semiconductor substrate are defined; (b) forming a first gate insulating film over the first region and the element separation portion; (c) forming a second gate insulating film over the second region and the element separation portion; (d) forming a first dummy gate over the first and second gate insulating films; (e) forming an interlayer insulating film over the first and second regions in order to cover the first dummy gate; (f) after the step (e), etching the interlayer insulating film, thereby a top surface of the first dummy gate is exposed; (g) after the step (f), removing the first dummy gate; (h) after the step (g), forming a first metal film over the first and second gate insulating films; and (i) after the step (h), etching the first metal film, thereby a top surface of the interlayer insulating film is exposed, wherein the first MISFET includes the first gate insulating film and the first metal film, wherein the second MISFET includes the second gate insulating film and the first metal film, wherein the first gate insulating film is a different film from the second gate insulating film, and wherein, on the element separation portion interposed between the first region and the second region, a boundary of the first and second gate insulating films is located on a side of the first gate insulating film.
6. A method of manufacturing a semiconductor device according to the claim 5 , wherein the first and second MISFETs constitute a CMOS invertors.
7. A method of manufacturing a semiconductor device according to the claim 5 , wherein the first gate insulating film includes Hf, O and La, and wherein the second gate insulating film includes Hf and O and does not include La.
8. A method of manufacturing a semiconductor device according to the claim 5 , wherein the first metal film includes Al.
9. A method of manufacturing a semiconductor device including a first MISFET and a second MISFET, comprising steps of: (a) forming an element separation portion in a semiconductor substrate, thereby first and second regions of the semiconductor substrate are defined; (b) forming a first gate insulating film over the first region and the element separation portion; (c) forming a second gate insulating film over the second region and the element separation portion; (d) forming an interlayer insulating film over the first and second regions; (e) forming a first trench in the interlayer insulating film, the first trench arranged over the first and second gate insulating film; and (f) embedding a first metal film in the first trench, wherein the first MISFET includes the first gate insulating film and the first metal film, wherein the second MISFET includes the second gate insulating film and the first metal film, wherein the first gate insulating film is a different film from the second gate insulating film, and wherein, on the element separation portion interposed between the first region and the second region, a boundary of the first and second gate insulating films is located on a side of the first gate insulating film.
10. A method of manufacturing a semiconductor device according to the claim 9 , wherein the first and second MISFETs constitute a CMOS invertors.
11. A method of manufacturing a semiconductor device according to the claim 9 , wherein the first gate insulating film includes Hf, O and La, and wherein the second gate insulating film includes Hf and O and does not include La.
12. A method of manufacturing a semiconductor device according to the claim 9 , wherein the first metal film includes Al.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 13, 2015
January 12, 2016
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