A memory system includes a nonvolatile memory device, and a memory controller configured to control the nonvolatile memory device such that memory cells connected with a selected row of the nonvolatile memory device are programmed by one of a first program mode and a second program mode. At the first program mode, a plurality of logical pages corresponding in number to a maximum page number is stored at the memory cells, and at the second program mode, one or more logical pages the number of which is less than the maximum page number are stored at the memory cells using a bias condition that is different from that used in the first program mode.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory system, comprising: a nonvolatile memory device configured to program memory cells with multi-bit data during a program cycle; and a memory controller configured to control the nonvolatile memory device such that memory cells connected with a selected row of the nonvolatile memory device are programmed in accordance with a write command by one of a first program mode and a second program mode, wherein at the first program mode, a plurality of logical pages corresponding in number to a maximum page number is stored at the memory cells; and wherein at the second program mode, one or more logical pages the number of which is less than the maximum page number are stored at the memory cells using a bias condition that is different from that used in the first program mode, wherein at the second program mode, the memory cells are programmed to have an erase state or a pseudo program state, and the pseudo program state is allocated to be disposed between read voltages, having a widest voltage window, from among read voltages for reading a logical page mapped on the memory cells.
2. The memory system of claim 1 , wherein the logical pages corresponding in number to the maximum page number are respectively mapped when addresses of the memory cells are mapped in the first program mode; and wherein at least one of the logical pages corresponding in number to the maximum page number is mapped out in the second program mode.
3. The memory system of claim 2 , wherein at the first program mode, two logical pages are allocated to the memory cells; and wherein at the second mode, an MSB page among the two logical pages is allocated for address mapping and an LSB page among the two logical pages is mapped out.
4. The memory system of claim 1 , wherein at the first program mode, three logical pages are allocated to the memory cells; and wherein at the second program mode, one of LSB and MSB pages among the three logical pages is allocated for address mapping.
5. The memory system of claim 4 , wherein the pseudo program state comprises first pseudo program states, and at the second program mode, the memory cells are programmed to have the erase state and the first pseudo program states.
6. The memory system of claim 5 , wherein each of the first pseudo program states is allocated to be disposed between read voltages, having the widest voltage window, from among read voltages for respectively reading logical pages mapped on the memory cells.
7. The memory system of claim 2 , wherein at the first program mode, three logical pages are allocated to the memory cells; and wherein at the second program mode, LSB and MSB pages of the three logical pages are allocated for address mapping.
8. The memory system of claim 7 , wherein the pseudo program state comprises first, second and third pseudo program states, and at the second program mode, the memory cells are programmed to have one of the erase state, the first pseudo program state, the second pseudo program state, and the third pseudo program state.
9. The memory system of claim 1 , wherein at the first program mode, four logical pages are allocated to the memory cells; and wherein at the second program mode, an LSB page among the four logical pages is allocated for address mapping.
10. The memory system of claim 9 , wherein the pseudo program state comprises a first pseudo program state, and at the second program mode, the memory cells are programmed to have the erase state and the first pseudo program state.
11. The memory system of claim 10 , wherein the first pseudo program state is allocated to be disposed between read voltages, having the widest voltage window, from among read voltages for reading a logical page mapped on the memory cells.
12. The memory system of claim 1 , wherein at the first program mode, four logical pages are allocated to the memory cells at a mapping table; and wherein at the second program mode, at least two logical pages, including an MSB page, among the four logical pages are allocated for address mapping.
13. The memory system of claim 12 , wherein the pseudo program state comprises first, second and third pseudo program states, and at the second program mode, the memory cells are programmed to have one of the erase state, the first pseudo program state, the second pseudo program state, and the third pseudo program state.
14. The memory system of claim 1 , wherein the bias condition includes at least one of an increment of a program voltage, a start program voltage, a number of verification voltage pulses and a number of program loops of each of the first and second program modes.
15. A memory system, comprising: a nonvolatile memory device including a memory cell array and configured to program logical N-pages of data in memory cells connected to a same word line of the memory cell array, where N is an integer of two or more; a memory controller configured to receive an externally supplied write command and write requested data, and to control the nonvolatile memory device in a selected one of a normal program mode and a pseudo program mode, wherein in the normal program mode, the memory controller controls the nonvolatile memory device to store the write requested data as N-bit data in the memory cells connected to the same word line of the memory cell array, and wherein in the pseudo program mode, the memory controller controls the nonvolatile memory device to store the write requested data as less-than-N-bit data in the memory cells connected to the same word line of the memory cell array, and wherein at least one bias condition of the pseudo program mode is different from at least one bias condition of the normal program mode such that a program speed of the pseudo program mode is greater than a program speed of the normal program mode.
16. The memory system of claim 15 , wherein the memory controller comprises a mapping table mapping the N-logical pages, and wherein the memory controller is configured to map out, in the mapping table, logical pages among the N-logical pages that are not allocated in the pseudo program mode.
17. The memory system of claim 15 , wherein the normal program mode or the pseudo program mode is selected based on at least one of a size, an attribute and a relative importance of the write requested data.
18. A program method of a nonvolatile memory device which programs plural pages of data in a one-shot program mode, comprising: comparing a size of write requested data with a reference size; issuing a pseudo program command on the write requested data to the nonvolatile memory device when a size of the write requested data is smaller than the reference size; programming selected memory cells with the write requested data under a pseudo program mode in accordance with the pseudo program command; and mapping out a page address of a logical page area, excluded by the pseudo program mode, from among a plurality of logical page areas included in the selected memory cells at a mapping table, wherein a program state of memory cells formed according to the pseudo program mode has a characteristic threshold voltage distribution that is different from a characteristic threshold voltage distribution formed according to the one-shot program mode, and at least one bias condition of the pseudo program mode is set so that a program speed of the pseudo program mode is greater than a program speed of the one-shot program mode.
19. The program method of claim 18 , wherein the program state of memory cells formed according to the pseudo program mode includes an erase state and at least one pseudo program state, the at least one pseudo program state being disposed between read voltages, forming a widest voltage window, from among read voltages of an allocated logical page.
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January 23, 2014
January 26, 2016
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