An integrated circuit device includes a dielectric layer disposed onto a first substrate, the dielectric layer having a sacrificial cavity formed therein. The circuit also includes a membrane layer formed onto the dielectric layer and suspended over the sacrificial cavity, and a capping substrate bonded to the membrane layer such that a second cavity is formed, the second cavity being connected to the sacrificial cavity though a via formed into the membrane layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated circuit device comprising: a dielectric layer disposed onto a first substrate, the dielectric layer having a sacrificial cavity formed therein; a membrane layer formed onto the dielectric layer and suspended over the sacrificial cavity; and a capping substrate bonded to the membrane layer such that a second cavity is formed, the second cavity being connected to the sacrificial cavity though a via formed into the membrane layer.
2. The device of claim 1 , wherein the first substrate comprises a thru-silicon via that connects to a metal bonding pad formed on an opposite side of the first substrate from the dielectric layer.
3. The device of claim 2 , further comprising a CMOS substrate eutectically bonded to the metal bonding pad.
4. The device of claim 1 , further comprising a bottom electrode layer at a bottom of the sacrificial cavity and a top electrode layer at a top of the sacrificial cavity.
5. The device of claim 4 , wherein a conductive element of the top electrode layer extends over the sacrificial cavity.
6. The device of claim 1 , wherein the first substrate is a high resistive substrate having a resistance of at least 1000 ohm-cm.
7. The device of claim 1 , wherein the capping layer is fusion bonded to a thin dielectric layer formed on the membrane layer.
8. The device of claim 1 , further comprising a thin dielectric layer on the inner walls of the sacrificial cavity.
9. The device of claim 1 , further comprising, a suspended portion of the membrane layer between the sacrificial cavity.
10. The device of claim 9 , wherein suspended portion comprises a Radio Frequency (RF) switch device.
11. An integrated circuit device comprising: a dielectric layer disposed onto a first substrate, the dielectric layer having a sacrificial cavity formed therein, wherein the first substrate includes a thru-silicon via; a top electrode layer on top of the sacrificial cavity; a bottom electrode layer on bottom of the sacrificial cavity; a membrane layer formed onto the dielectric layer; a capping substrate bonded to the membrane layer such that a second cavity is formed, the second cavity being connected to the sacrificial cavity though a via formed into the membrane layer; and a CMOS substrate connected to an opposite side of the first substrate from the dielectric layer through a eutectic bond and being electrically connected to the first substrate through the thru-silicon via.
12. An integrated circuit device comprising: a dielectric layer on a first substrate; a first cavity formed into the dielectric layer; a membrane layer over the dielectric layer and the first cavity; at least one opening through the membrane layer; and a capping substrate that is fusion bonded to the membrane layer such that a second cavity is formed, the second cavity being connected to the first cavity though the at least one opening through the membrane layer.
13. The device of claim 12 , further comprising a thru-silicon via in the first substrate beneath the dielectric layer.
14. The device of claim 13 , further comprising, a metal pad on an opposite side of the first substrate from the dielectric layer, the metal pad being connected to the thru-silicon via.
15. The device of claim 14 , further comprising a Complementary Metal Oxide Semiconductor (CMOS) substrate that is eutectically bonded to the metal pad.
16. The device of claim 12 , further comprising, a bottom electrode layer at a bottom of the first cavity and a top electrode layer at a top of the first cavity.
17. The device of claim 16 , wherein a conductive element of the top electrode layer extends over the first cavity.
18. The device of claim 12 , wherein the first substrate is a high resistive substrate having a resistance of at least 1000 ohm·cm.
19. The device of claim 12 , further comprising a thin dielectric layer deposited on the first cavity.
20. The device of claim 12 , wherein a portion of the membrane layer is suspended between the first cavity and the second cavity.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 11, 2013
February 9, 2016
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