A control integrated circuit for a power factor correction converter has a pin for detecting an alternating-current information and a direct-current information of an input signal. The control integrated circuit comprises a signal peak detector for detecting a peak value of the input signal to the pin to obtain the direct-current information of the input signal. Since the alternating-current information and the direct-current information of the input signal can be obtained through the same pin, the pin count of the control integrated circuit can be decreased.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A control integrated circuit for a power factor correction converter, comprising: a pin configured to receive an input signal for the control integrated circuit to obtain an alternating-current information of the input signal; and a signal peak detector connected to the pin, configured to detect a peak of the input signal to generate an output peak signal having a direct-current information of the input signal, the signal peak detector comprising: a first comparator connected to the pin, configured to generate a comparison signal when the input signal is greater than an internal peak signal; a first counter connected to the first comparator, configured to increase a count it outputs according to the comparison signal and reset the count responsive to a resetting signal; a first digital-to-analog converter connected to the first comparator and the first counter, configured to convert the count into the internal peak signal; a storage unit connected to the first counter, configured to obtain from the first counter and store the count in response to a sampling signal; a second comparator connected to the pin, configured to generate the sampling signal when the input signal is lower than a reference voltage, and generate the resetting signal when the sampling signal ends; and a second digital-to-analog converter connected to the storage unit, configured to convert the count stored in the storage unit into the output peak signal.
2. The control integrated circuit of claim 1 , wherein a working frequency of the first and second comparators is determined by a clock.
3. The control integrated circuit of claim 1 , wherein the storage unit comprises: a switch connected to the first counter, configured to be turned on responsive to the sampling signal; and a second counter connected to the first counter through the switch, and connected to the second digital-to-analog converter, configured to obtain from the first counter and store the count when the switch is turned on.
4. A control integrated circuit for a power factor correction converter, comprising: a pin configured to receive an input signal for the control integrated circuit to obtain an alternating-current information of the input signal; and a signal peak detector connected to the pin, configured to detect a peak of the input signal to generate an output peak signal having a direct-current information of the input signal, the signal peak detector comprising: a comparator connected to the pin, configured to compare the input signal with the output peak signal to generate a rising signal or a falling signal; a counter connected to the comparator, configured to increase and decrease a count it outputs according to the rising signal and the falling signal, respectively; and a digital-to-analog converter connected to the comparator and the counter, configured to convert the count into the output peak signal; wherein the count is increased in a first frequency and is decreased in a second frequency lower than the first frequency.
5. The control integrated circuit of claim 4 , further comprising a clock generator connected to the comparator, configure to provide a first clock having the first frequency when receiving the rising signal, so as to determine a working frequency for the comparator, and provide a second clock having the second frequency when receiving the falling signal, so as to determine the working frequency for the comparator.
6. A signal peak detector for detecting a peak of an input signal to generate an output peak signal, comprising: a first comparator configured to generate a comparison signal when the input signal is higher than an internal peak signal; a first counter connected to the first comparator, configured to increase a count it outputs according to the comparison signal, and reset the count according to a resetting signal; a first digital-to-analog converter connected to the first comparator and the first counter, configured to convert the count into the internal peak signal; a storage unit connected to the first counter, configured to obtain from the first counter and store the count according to a sampling signal; a second comparator connected to the first counter and the storage unit, configured to generate the sampling signal when the input signal is lower than a reference voltage, and generate the resetting signal when the sampling signal ends; and a second digital-to-analog converter connected to the storage unit, configured to convert the count stored in the storage unit into the output peak signal.
7. The signal peak detector of claim 6 , wherein a working frequency of the first and second comparators is determined by a clock.
8. The signal peak detector of claim 6 , wherein the storage unit comprises: a switch connected to the first counter, configured to be turned on responsive to the sampling signal; and a second counter connected to the first counter through the switch, and connected to the second digital-to-analog converter, configured to obtain from the first counter and store the count when the switch is turned on.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 23, 2013
February 9, 2016
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.