Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells. One such sub-block may comprise a vertical string of memory cells including a select transistor. An apparatus may include a sub-block disabling circuit. The sub-block disabling circuit may include a content-addressable memory. The content-addressable memory may receive an address, including a block address and a sub-block address. The content addressable memory may output a signal to disable a tagged sub-block if the received address includes the block address and the sub-block address associated with the tagged sub-block. The sub-block disabling circuit may further include a plurality of drivers to drive one or more of the select transistors based on the signal. Other apparatus and methods are described.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus comprising: a plurality of blocks of memory cells, at least one of the plurality of blocks including two or more sub-blocks; a sub-block disabling circuit including a memory to store a block address and sub-block address associated with a sub-block determined to be defective, wherein the sub-block disabling circuit is configured to disable a sub-block associated with the stored block address and sub-block address responsive to receiving a block address and sub-block address that matches the stored block address and sub-block address, and the sub-block disabling circuit further comprises a drain select gate (SGD) driver, wherein the sub-block disabling circuit is configured to disable the sub-block associated with the stored block address and sub-block address responsive to receiving a block address and sub-block address that matches the stored block address and sub-block address.
2. The apparatus of claim 1 , wherein the sub-block disabling circuit is configured to disable the SGD driver responsive to receiving a block address and sub-block address that matches the stored block address and sub-block address.
3. The apparatus of claim 1 , further comprising: a block disabling circuit including a latch, the latch to store a tag status of a block and the latch arranged to receive a block selection signal and output a block enablement signal based on the tag status of the block.
4. The apparatus of claim 1 , wherein each block of the plurality of blocks of memory cells is associated with at least four access lines, each of the at least four access lines being located in a different tier of a semiconductor construction.
5. The apparatus of claim 1 , wherein the apparatus comprises a memory device.
6. The apparatus of claim 5 , wherein the apparatus comprises a three-dimensional NOT AND (NAND) memory device.
7. The apparatus of claim 1 , wherein the sub-block disabling circuit is configured to disable a plurality of sub-blocks.
8. The apparatus of claim 7 , wherein the sub-block disabling circuit is configured to disable one half the sub-blocks in a block.
9. A method for controlling access to a memory device, the method comprising: receiving a sub-block address; determining whether the received sub-block address match a stored sub-block address, wherein the stored sub-block address is associated with a sub-block of memory cells determined to be defective; and responsive to determining the received sub-block address matches the stored sub-block address, disabling a block associated with the stored sub-block address if a threshold number of sub-blocks associated with a block associated with the sub-block address have been tagged as defective.
10. The method of claim 9 , wherein determining whether the received sub-block address matches a stored sub-block address comprises determining whether the received sub-block address matches a sub-block address stored in a memory.
11. The method of claim 10 , wherein determining whether the received sub-block address matches a sub-block address stored in a memory comprises determining whether the received sub-block address matches a sub-block address stored in a content-addressable memory.
12. The method of claim 11 , further comprising: receiving a block address; and determining whether the received block address matches a stored block address that was stored in a second memory separate from the content-addressable memory.
13. The method of claim 9 , further comprising: generating a count of sub-block of memory cells that were tagged as defective in the block based on matches with stored sub-block addresses; and disabling only the sub-block associated with the stored sub-block address if the count is less than the threshold number of sub-blocks of the associated block were tagged as defective.
14. The method of claim 9 , further comprising: generating a count of sub-block of memory cells that were tagged as defective in the block based on matches with stored sub-block addresses; and disabling one half of the sub-blocks associated with the block if less than the threshold number of sub-blocks of the associated block were tagged as defective.
15. An apparatus comprising: a plurality of blocks of memory cells, at least one of the plurality of blocks including two or more sub-blocks; and a memory controller including a memory to store a block address and a sub-block address associated with a sub-block of the memory device determined to be defective, wherein the memory controller further comprises a second memory for storing a block address associated with a block of the memory device determined to be defective.
16. The apparatus of claim 15 , wherein the memory controller is configured to examine the memory to determine if a block address and sub-block address of a received user address matches a block address and sub-block address stored in the memory; and disable a sub-block associated with a block address and sub-block address stored in the memory responsive to determining that a block address and sub-block address of a received user address matches the block address and sub-block address stored in the memory.
17. The apparatus of claim 16 , wherein the memory controller is configured to disable a plurality of sub-blocks responsive to determining that the block address and sub-block address of a received user address matches the block address and sub-block address stored in the memory.
18. The apparatus of claim 15 , wherein the plurality of blocks of memory cells are included in a three-dimensional NOT AND (NAND) memory device.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 9, 2015
February 16, 2016
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