A printed circuit board (PCB) assembly includes a PCB having a core substrate, a plurality of conductive traces on a first surface of the PCB, and a ground layer on the second surface of the PCB. The conductive traces comprise a pair of differential signal traces. An intervening reference trace is disposed between the differential signal traces. A connector is disposed at one end of the plurality of conductive traces. A semiconductor package is mounted on the first surface at the other end of the plurality of conductive traces.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A leadframe package, comprising: a die pad; a semiconductor die mounted on the die pad; a plurality of leads disposed in a first horizontal plane along peripheral edges of the die pad; a reference inner lead intervening between two adjacent, successive high-speed signal leads of the leads; a ground bar downset from the first horizontal plane to a second horizontal plane and connected to the die pad with a downset bridge; a plurality of tie bars extending outward from the die pad; a plurality of first bonding wires for electrically connecting the semiconductor die to the leads respectively; and a molding compound encapsulating the semiconductor die, the first bonding wires, the leads, the ground bar, the tie bars, and the die pad, wherein an outer end of the reference inner lead is encapsulated by the molding compound.
2. The leadframe package according to claim 1 wherein each of the leads comprises an inner lead with a length L, and wherein the reference inner lead has a length greater than or equal to about one-third the length L of the high-speed signal leads.
3. The leadframe package according to claim 1 , wherein the reference inner lead is completely embedded within the molding compound.
4. The leadframe package according to claim 1 , wherein the reference inner lead is electrically connected to a ground or power net of the semiconductor die.
5. The leadframe package according to claim 1 , further comprising a plurality of second bonding wires for electrically connecting the ground bar to the semiconductor die.
6. The leadframe package according to claim 1 , wherein an inner end of the reference inner lead is integral with the ground bar with a downset bridge between the inner end and the ground bar.
7. The leadframe package according to claim 1 , wherein an inner end of the reference inner lead is integral with at least one of the tie bars.
8. The leadframe package according to claim 1 , wherein a bottom surface of the die pad is exposed.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 13, 2013
February 23, 2016
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