A semiconductor device includes a semiconductor substrate including a trench, a gate insulation film located over a bottom and sidewall of the trench, a first gate formed over the gate insulation film and in a lower portion of the trench, a second gate formed over the first gate and in an upper portion of the trench, a multi-layered structure provided between the gate insulation film and the second gate.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: a semiconductor substrate including a trench; a gate insulation film located over a bottom and sidewall of the trench; a first gate formed over the gate insulation film and in a lower portion of the trench; a second gate formed over the first gate and in an upper portion of the trench, wherein the first gate is electrically connected to the second gate; and a multi-layered structure including a nitride film and an oxide film provided between the gate insulation film and the second gate, wherein an interface layer between the nitride film pattern and the insulation film pattern includes a plurality of positive charges.
2. The semiconductor device according to claim 1 , further comprising: a junction region formed in the semiconductor substrate adjacent to the trench.
3. The semiconductor device according to claim 2 , wherein the multi-layered structure is overlapped with the junction region.
4. The semiconductor device according to claim 1 , wherein the multi-layered structure includes a bi-layer structure of the nitride film and the oxide film.
5. The semiconductor device according to claim 1 , wherein the multi-layered structure includes a plurality of nitride films and a plurality of oxide films which are alternately repeated.
6. A semiconductor device comprising: a semiconductor substrate including a trench; a gate insulation film located over a bottom and sidewall of the trench; a junction region formed in the semiconductor substrate adjacent to the trench; a gate formed over the gate insulation film and in the trench; and a multi-layered structure including a nitride film and an oxide film formed between the gate insulation film and the gate, wherein the multi-layered structure is overlapped with the junction region, wherein an interface between the nitride film pattern and the insulation film pattern includes a plurality of positive charges.
7. The semiconductor device according to claim 6 , wherein the multi-layered structure includes a bi-layer structure of a nitride film and an oxide film.
8. The semiconductor device according to claim 6 , wherein the multi-layered structure includes a plurality of nitride films and a plurality of oxide films which are alternately repeated.
9. A semiconductor device comprising: a gate; a junction; and a multi-layered structure provided between the gate and the junction, wherein the multi-layered structure includes a stack of an oxide film and a nitride film, and wherein an interface between the oxide film and the nitride film including a positive charge, wherein the multi-layered structure is overlapped with the junction.
10. The semiconductor device of claim 9 , wherein the nitride film is a nitrogen-excessive nitride film.
11. The semiconductor device of claim 9 , wherein the gate is a buried gate including a first gate and a second gate, wherein the second gate is formed over the first gate, and wherein the multi-layered structure overlapped with the junction.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 24, 2014
February 23, 2016
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