A video decoder, method and computer program product allow for processing of a video frame encoded in rectangular tiles. An interface receives a bit stream in tile order within a video frame that was encoded into rectangular tiles. A processor decodes the video frame while respecting dependency breaks at tile boundaries; the rectangular tiles include an integer number of two-dimensional blocks of pixels. A tile shape is defined by N×M two-dimensional blocks of pixels, respective values of N and M need not be identical for each of the rectangular tiles, and information regarding tile shape for each tile being conveyed from an encoder to the decoder. The decoder determines N and M for each tile from the information, and tiles have dependency breaks therebetween.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A video decoder, comprising: an interface configured to receive a bit stream in tile order within a video frame that was encoded into rectangular tiles; and processing circuitry configured to decode the video frame while respecting dependency breaks at tile boundaries, wherein the rectangular tiles including an integer number of two-dimensional blocks of pixels, a tile shape of each of the rectangular tiles being defined by N×M two-dimensional blocks of pixels, respective values of N and M need not be identical for each of the rectangular tiles, and information regarding tile shape being conveyed from an encoder to the decoder, the decoder configured to determine the values of N and M for each tile from the information, the rectangular tiles having dependency breaks therebetween; wherein the processing circuitry is configured to process a maximum number of horizontal tiles and a maximum number of vertical tiles independent of a resolution of video frames, wherein the resolution of the video frames is determined by a width of the video frames and a height of the video frames.
2. The video decoder of claim 1 , wherein the processing circuitry is configured to support decoding according to level 3.1 of the High Efficiency Video Coding (HEVC) standard, wherein the maximum number of vertical tiles of 3 and the maximum number of horizontal tiles of 3.
3. The video decoder of claim 2 , wherein, the processing circuitry is configured to support a maximum picture size of 983,040 samples.
4. The video decoder of claim 1 , wherein the maximum number of horizontal tiles is 5.
5. The video decoder of claim 4 , wherein the processing circuitry is configured to support level decoding according to level 4 and level 4.1 of the High Efficiency Video Coding (HEVC) standard, with an associated maximum number of vertical tiles and maximum number of horizontal tiles.
6. The video decoder of claim 4 , wherein the processing circuitry is configured to support a maximum bit rate of 30,000 (1000 bits/sec) and 5 vertical tiles.
7. The video decoder of claim 4 , wherein the processing circuitry is configured to support a maximum bit rate of 50,000 (1000 bits/sec) and 5 vertical tiles.
8. The video decoder of claim 1 , wherein the processing circuitry supports decoding according to level 2 of the High Efficiency Video Coding (HEVC) standard, with an associated maximum number of vertical tiles and maximum number of horizontal tiles.
9. The video decoder of claim 1 , wherein the processing circuitry supports decoding according to level 3 of the High Efficiency Video Coding (HEVC) standard, with an associated maximum number of vertical tiles and maximum number of horizontal tiles.
10. The video decoder of claim 9 , wherein the processing circuitry processes the associated maximum number of vertical tiles and maximum number of horizontal tiles independent of the resolution of the video frames.
11. The video decoder of claim 1 , wherein the processing circuitry supports decoding according to the High Efficiency Video Coding (HEVC) standard of at least one of level 5, level 5.1, and level 5.2, with an associated maximum number of vertical tiles and maximum number of horizontal tiles.
12. The video decoder of claim 1 , wherein the processing circuitry supports decoding according to the High Efficiency Video Coding (HEVC) standard of at least one of level 6, level 6.1, and level 6.2, with an associated maximum number of vertical tiles and maximum number of horizontal tiles.
13. A video decoding method, comprising: receiving a bit stream in tile order within a video frame that was encoded into rectangular tiles; preparing to process a maximum number of horizontal tiles and a maximum number of vertical tiles independent of a resolution of video frames, wherein the resolution of the video frames is determined by a width of the video frames and a height of the video frames, wherein the maximum number of horizontal tiles and the maximum number of vertical tiles are known to an encoder in advance either by the encoder having a preregistered indication of tiles, or by a decoder informing the encoder in advance; and decoding with processing circuitry at least part of the video frame while respecting dependency breaks at tile boundaries, wherein the rectangular tiles including an integer number of two-dimensional blocks of pixels, a tile shape of the rectangular tiles being defined by N×M two-dimensional blocks of pixels, respective values of N and M need not be identical for each of the rectangular tiles, the receiving an indication including receiving information regarding tile size, and the decoding including determining the values of N and M for each tile from the information, the rectangular tiles having dependency breaks therebetween.
14. The video decoding method of claim 13 , wherein the decoding is compliant with level 3.1 of the High Efficiency Video Coding (HEVC) standard, and wherein the maximum number of vertical tiles is 3 and the maximum number of horizontal tiles is 3.
15. The video decoding method of claim 14 , wherein the decoding supports a maximum picture size of 983,040 samples.
16. The video decoding method of claim 13 , wherein the maximum number of horizontal tiles is 5.
17. The video decoding method of claim 16 , wherein the decoding is compliant with level 4 and level 4.1 of the High Efficiency Video Coding (HEVC) standard.
18. The video decoding method of claim 16 , wherein the decoding supports a maximum bit rate of 30,000 (1000 bits/sec) and 5 vertical tiles.
19. The video decoding method of claim 16 , wherein the decoding supports a maximum bit rate of 50,000 (1000 bits/sec) and 5 vertical tiles.
20. The video decoding method of claim 13 , wherein the decoding supports decoding according to level 2 of the High Efficiency Video Coding (HEVC) standard, with an associated maximum number of vertical tiles and maximum number of horizontal tiles.
21. The video decoding method of claim 13 , wherein the decoding supports decoding according to level 3 of the High Efficiency Video Coding (HEVC) standard, with an associated maximum number of vertical tiles and maximum number of horizontal tiles.
22. The video decoding method of claim 13 , wherein the decoding supports decoding according to the High Efficiency Video Coding (HEVC) standard of at least one of level 5, level 5.1, and level 5.2, with an associated maximum number of vertical tiles and maximum number of horizontal tiles.
23. The video decoding method of claim 13 , wherein the decoding supports decoding according to the High Efficiency Video Coding (HEVC) standard of at least one of level 6, level 6.1, and level 6.2, with an associated maximum number of vertical tiles and maximum number of horizontal tiles.
24. A non-transitory computer program product embodied with a computer program that when executed by processing circuitry implements a method, the method comprising: receiving a bit stream in tile order within a video frame that was encoded into rectangular tiles; preparing to process a maximum number of horizontal tiles and a maximum number of vertical tiles independent of a resolution of video frames, wherein the resolution of the video frames is determined by a width of the video frames and a height of the video frames, wherein the maximum number of horizontal tiles and the maximum number of vertical tiles are known to an encoder in advance either by the encoder having a preregistered indication of maximum number of horizontal and vertical tiles, or by the decoder informing the encoder in advance; and decoding with the processing circuitry at least part of the video frame while respecting dependency breaks at tile boundaries, wherein the rectangular tiles including an integer number of two-dimensional blocks of pixels, a tile shape of the rectangular tiles being defined by N×M two-dimensional blocks of pixels, respective values of N and M need not be identical for each of the rectangular tiles, the receiving an indication including receiving information regarding tile size, and the decoding including determining the values of N and M for each tile from the information, the rectangular tiles having dependency breaks therebetween.
25. The non-transitory computer program product of claim 24 , wherein the decoding is compliant with level 3 of the High Efficiency Video Coding (HEVC) standard, and wherein the maximum number of vertical tiles of 3 and the maximum number of horizontal tiles of 3.
26. The non-transitory computer program product of claim 25 , wherein, the decoding supports a maximum picture size of 983,040 samples.
27. The non-transitory computer program product of claim 24 , wherein the decoding supports a maximum number of horizontal tiles of 5.
28. The non-transitory computer program product of claim 26 , wherein the decoding is compliant with level 4 and level 4.1 of the High Efficiency Video Coding (HEVC) standard.
29. The non-transitory computer program product of claim 26 , wherein the decoding supports a maximum bit rate of 30,000 (1000 bits/sec) and 5 vertical tiles.
30. The non-transitory computer program product of claim 24 , wherein the decoding supports decoding according to level 2 of the High Efficiency Video Coding (HEVC) standard, with an associated maximum number of vertical tiles and maximum number of horizontal tiles.
31. The non-transitory computer program product of claim 24 , wherein the decoding supports decoding according to level 3 of the High Efficiency Video Coding (HEVC) standard, with an associated maximum number of vertical tiles and maximum number of horizontal tiles.
32. The non-transitory computer program product of claim 24 , wherein the decoding supports decoding according to the High Efficiency Video Coding (HEVC) standard of at least one of level 5, level 5.1, and level 5.2, with an associated maximum number of vertical tiles and maximum number of horizontal tiles.
33. The non-transitory computer program product of claim 24 , wherein the decoding supports decoding according to the High Efficiency Video Coding (HEVC) standard of at least one of level 6 , level 6.1, and level 6.2, with an associated maximum number of vertical tiles and maximum number of horizontal tiles.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 15, 2013
February 23, 2016
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.