Semiconductor memory device and operating method thereof

1. An operating method of a semiconductor memory device which comprises cell strings comprising a plurality of source select transistors electrically coupled to a common source line in series, at least one drain select transistor electrically coupled to a bit line, and memory cells electrically coupled between the at least one drain select transistor and the source select transistors, wherein the operating method comprises: programming a second source select transistor electrically coupled to the common source line through a first source select transistor; reprogramming the second source select transistor when a threshold voltage of the second source select transistor is less than a target voltage; and ending a program with respect to the second source select transistor when the threshold voltage of the second source select transistor is greater than or equal to the target voltage, wherein the programming comprises: applying a program permission voltage to the bit line; turning on the at least one drain select transistor and the memory cells and transmitting the program permission voltage to the second source select transistor; turning off the first source select transistor and electrically decoupling the second source select transistor from the common source line; and applying a program voltage to the second source select transistor and increasing the threshold voltage of the second source select transistor.

2. The operating method of claim 1 , further comprising: shadow-programming the first source select transistor before the programming such that a threshold voltage of the first source select transistor is increased.

3. The operating method of claim 2 , wherein the shadow-programming comprises: applying a reference voltage to the at least one drain select transistor, the memory cells, and the second source select transistor; and applying a second program voltage to a gate of the first source select transistor to increase a threshold voltage of the first source select transistor.

4. The operating method of claim 2 , wherein the shadow-programming comprises: floating the at least one drain select transistor, the memory cells, and the second source select transistor; and applying a second program voltage to a gate of the first source select transistor to increase a threshold voltage of the first source select transistor.

5. The operating method of claim 2 , wherein the shadow-programming comprises: turning on the at least one drain select transistor, the memory cells, and the second source select transistor; and applying a second program voltage to a gate of the first source select transistor to increase a threshold voltage of the first source select transistor.

6. The operating method of claim 2 , further comprising: performing an erase operation on the first source select transistor after the programming of the second source select transistor.

7. The operating method of claim 1 , wherein the first source select transistor is electrically coupled to a first source select line, the second source select transistor is electrically coupled to a second source select line, the memory cells are electrically coupled to respective word lines, and the at least one drain select transistor is electrically coupled to a drain select line.

8. The operating method of claim 7 , wherein, in the electrical decoupling of the second source select transistor from the common source line, a common source line voltage having a positive voltage is applied to the common source line, and a turn off voltage smaller than or equal to the common source line voltage is applied to the first source select line and the first source select transistor is turned off.

9. The operating method of claim 8 , wherein the turn off voltage is a reference voltage, and a threshold voltage of the first source select transistor is a positive voltage.

10. The operating method of claim 7 , wherein the transmitting of the program permission voltage to the second source select transistor comprises: applying a drain select line voltage greater than the program permission voltage to the drain select line and turning on the at least one drain select transistor; and applying a word line voltage to the word lines and turning on the memory cells.

11. The operating method of claim 10 , wherein the memory cells are in an erase state, and the word line voltage is either a ground voltage or a positive voltage.

12. The operating method of claim 10 , wherein, in the ending of the program, a program inhibition voltage is applied to the bit line, and the program inhibition voltage is greater than or equal to the drain select line voltage.

13. The operating method of claim 1 , wherein the reprogramming comprises: applying the program permission voltage to the bit line; turning on the at least one drain select transistor and the memory cells and transmitting the program permission voltage to the second source select transistor; turning off the first source select transistor and electrically decoupling the second source select transistor from the common source line; and applying a voltage greater than the program voltage to a gate of the second source select transistor and increasing the threshold voltage of the second source select transistor.

14. An operating method of a semiconductor memory device which comprises cell strings each comprising at least one first source select transistor electrically coupled to a common source line, at least one second source select transistor electrically coupled to the common source line through the first source select transistor, at least one drain select transistor electrically coupled to a bit line, and memory cells electrically coupled between the at least one drain select transistor and the second source select transistor, wherein the operating method comprises: applying a program permission voltage or a program inhibition voltage to bit lines of the cell strings; applying a drain select line voltage greater than the program permission voltage and less than or equal to the program inhibition voltage to a drain select line electrically coupled to drain select transistors of the cell strings and turning on or turning off the drain select transistors; applying a word line voltage to memory cells of the cell strings; turning off first source select transistors of the cell strings; and applying a program voltage to gates of second source select transistors of the cell strings.

15. The operation method of claim 14 , wherein the first source select transistors undergo a shadow program operation before the second source select transistors are programmed.

16. The operating method of claim 14 , wherein, a common source line voltage having a positive voltage is applied to the common source line, and a turn off voltage less than or equal to the common source line voltage is applied to a first source select line electrically coupled to the first source select transistors and the first source select transistor is turned off.

17. The operating method of claim 16 , wherein the turn off voltage is a reference voltage, and a threshold voltage of the first source select transistor is greater than 0.

18. A semiconductor memory device, comprising: a cell string including a plurality of source select transistors electrically coupled to a common source line in series, at least one drain select transistor electrically coupled to a bit line, and memory cells electrically coupled between the at least one drain select transistor and the source select transistors; and a peripheral circuit configured to control the cell string, wherein the peripheral circuit is configured to program a second source select transistor electrically coupled to the common source line through a first source select transistor, the peripheral circuit being configured to reprogram the second source select transistor when a threshold voltage of the second source select transistor is less than a target voltage and configured to end a program with respect to the second source select transistor when the threshold voltage of the second source select transistor is greater than or equal to the target voltage, and the peripheral circuit applies a program permission voltage to the bit line during the programming, turns on the at least one drain select transistor and the memory cells and transmits the program permission voltage to the second source select transistor, turns off the first source select transistor and electrically decouples the second source select transistor from the common source line, and applies a program voltage to a gate of the second source select transistor and increases the threshold voltage of the second source select transistor.

19. The semiconductor memory device of claim 18 , wherein the peripheral circuit is configured to perform a shadow program operation on the first source select transistor before the programming.

20. The semiconductor memory device of claim 18 , wherein the peripheral circuit applies a common source line voltage having a positive voltage to the common source line, applies a turn off voltage less than or equal to the common source line voltage to a gate of the first source select transistor, and turns off the first source select transistor.