A semiconductor device includes a substrate; an inter layer dielectric disposed on the substrate; a TSV penetrating the substrate and the ILD. In addition, a plurality of shallow trench isolations (STI) is disposed in the substrate, and a shield ring is disposed in the ILD surrounding the TSV on the STI. During the process of forming the TSV, the contact ring can protect adjacent components from metal contamination.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device, comprising: a substrate; an ILD (inter layer dielectric) disposed on the substrate; a TSV (through silicon via) penetrating the substrate and the ILD; and a contact ring, disposed in the ILD and surrounding the TSV, wherein the contact ring comprises a hollowed center region completely therethrough, the contact ring is an entirely enclosed structure, and parts of the ILD are disposed between the contact ring and the TSV.
2. The semiconductor device of claim 1 , further comprising a metal trace disposed on a surface of the ILD, wherein the TSV contacts the metal trace.
3. The semiconductor device of claim 2 , wherein the contact ring is electrically connected to the metal trace.
4. The semiconductor device of claim 2 , further comprising a barrier layer disposed in the TSV, wherein the barrier layer substantially contacts the metal trace, and the barrier layer is located inside the ILD.
5. The semiconductor device of claim 1 , further comprising a liner disposed in the TSV, wherein the liner is only disposed in the substrate.
6. The semiconductor device of claim 1 , further comprising a gate structure disposed on the substrate, and the gate structure includes a metal gate, a polysilicon gate or a dummy gate.
7. The semiconductor device of claim 1 , further comprising at least a STI (shallow trench isolation) disposed in the substrate, wherein the contact ring is disposed on the STI.
8. A semiconductor device, comprising: a substrate; an ILD (inter layer dielectric) disposed on the substrate; a TSV (through silicon via) penetrating the substrate and the ILD; a contact ring disposed surrounding the TSV side by side lie within a same plane, the contact ring comprises a hollowed center region completely therethrough, the contact ring is an entirely enclosed structure, and parts of the ILD are disposed between the contact ring and the TSV; and a liner disposed in the TSV, wherein the liner is only disposed in the substrate.
9. The semiconductor device of claim 8 , further comprising a wherein the contact ring disposed in the ILD and surrounding the TSV and a plurality of STI (shallow trench isolation) disposed in the substrate, wherein and the contact ring is disposed on the STI.
10. The semiconductor device of claim 8 , further comprising a metal trace disposed on a surface of the ILD, wherein the TSV contacts the metal trace.
11. The semiconductor device of claim 10 , wherein the contact ring is electrically connected to the metal trace.
12. The semiconductor device of claim 10 , further comprising a barrier layer disposed in the TSV, wherein the barrier layer substantially contacts the metal trace, and the barrier layer is located inside the ILD.
13. The semiconductor device of claim 8 , further comprising a gate structure disposed on the substrate, wherein the gate structure includes a metal gate, a polysilicon gate or a dummy gate.
14. The semiconductor device of claim 1 , wherein a top surface of the contact ring and the TSV being even with respect to each other.
15. The semiconductor device of claim 8 , wherein a top surface of the contact ring and the TSV being even with respect to each other.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 19, 2012
March 1, 2016
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