Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In one embodiment, a memory device includes a memory cell of a memory device, a bit-line coupled to the memory cell, a word-line coupled to the memory cell, a bit-line electrode coupled to the bit-line, a word-line electrode coupled to the word-line, current-limiting circuitry of a selection module coupled to one of the word-line electrode and the bit-line electrode having a lower potential, the current-limiting circuitry to facilitate a selection operation of the memory cell by the selection module, sensing circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the sensing circuitry to perform a read operation of the memory cell, and write circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the write circuitry to perform a write operation of the memory cell. Other embodiments may be described and/or claimed.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus comprising: a memory cell of a memory device; a bit-line electrode coupled with a bit-line; a word-line electrode coupled with a word-line; and write circuitry coupled to the word-line electrode, the write circuitry to perform a write operation of the memory cell, wherein the apparatus is to provide a capacitance of the word-line electrode that is lower than a capacitance of the bit-line electrode, and a potential of the word-line electrode that is lower than a potential of the bit-line electrode.
2. The apparatus of claim 1 , further comprising: current-limiting circuitry of a selection module coupled with the word-line electrode, the current-limiting circuitry to facilitate a selection operation of the memory cell by the selection module.
3. The apparatus of claim 2 , wherein the current-limiting circuitry comprises a current-mirror circuit.
4. The apparatus of claim 2 , wherein the current-limiting circuitry comprises a transistor gate that is to limit a current of the word-line electrode to a maximum current level.
5. The apparatus of claim 1 , further comprising: sensing circuitry coupled with the word-line electrode, the sensing circuitry to perform a read operation of the memory cell.
6. The apparatus of claim 1 , further comprising: a bit-line coupled with the memory cell and the bit-line electrode; and a word-line coupled with the memory cell and the word-line electrode.
7. The apparatus of claim 6 , wherein the memory cell is a memory cell of a three-dimensional array of memory cells, the word-line is a first word-line extending in a first dimension of the three-dimensional array, the bit-line extends in a second dimension of the three-dimensional array, and the memory cell is a first memory cell, the apparatus further comprising: a second memory cell of the three-dimensional array of memory cells, the second memory cell being in a stacked configuration with the first memory cell in a third dimension of the three-dimensional array; and a second word-line coupled to the word-line electrode and further coupled to the second memory cell, wherein the bit-line extends between the first word-line and the second word-line.
8. The apparatus of claim 6 , wherein: the memory cell, the bit-line, and the word-line are part of a tile comprising a plurality of memory cells, bit-lines, and word-lines; the tile has a first linear dimension that extends in a direction that is parallel to a lengthwise dimension of the bit-line; the tile has a second linear dimension that extends in a direction that is parallel to a lengthwise dimension of the word-line; the first linear dimension is greater than the second linear dimension; and the tile comprises a same number of bit-lines and word-lines.
9. The apparatus of claim 1 , wherein the write circuitry comprises a current profile generator to generate a current profile for a set or reset operation of the memory cell.
10. The apparatus of claim 5 , wherein the sensing circuitry comprises a voltage comparator.
11. The apparatus of claim 1 , wherein the memory device is a phase change memory and switch (PCMS) device.
12. An apparatus comprising: a first memory cell of a three-dimensional array of memory cells; a bit-line coupled to the first memory cell; a first word-line coupled to the first memory cell; a bit-line electrode coupled to the bit-line; a word-line electrode coupled to the first word-line; and current-limiting circuitry of a selection module coupled to the word-line electrode, the current-limiting circuitry to facilitate a selection operation of the first memory cell by the selection module; wherein the apparatus is to provide a potential of the word-line electrode that is lower than a potential of the bit-line electrode, and wherein the first word-line extends in a first dimension of the three-dimensional array and the bit-line extends in a second dimension of the three-dimensional array, the apparatus further comprising: a second memory cell of the three-dimensional array of memory cells, the second memory cell being in a stacked configuration with the first memory cell in a third dimension of the three-dimensional array; and a second word-line coupled to the word-line electrode and further coupled to the second memory cell, wherein the bit-line extends between the first word-line and the second word-line.
13. The apparatus of claim 12 , wherein the current-limiting circuitry comprises a current-mirror circuit.
14. The apparatus of claim 12 , further comprising: sensing circuitry coupled to the word-line electrode, the sensing circuitry to perform a read operation of the first and second memory cells.
15. The apparatus of claim 12 , further comprising: write circuitry coupled to the word-line electrode, the write circuitry to perform a write operation of the first and second memory cells.
16. An apparatus comprising: a memory cell of a memory device; a bit-line coupled to the memory cell; a word-line coupled to the memory cell; a bit-line electrode coupled to the bit-line; a word-line electrode coupled to the word-line; and sensing circuitry coupled to the word-line electrode, the sensing circuitry to perform a read operation of the memory cell, wherein: the apparatus is to provide a potential of the word-line electrode that is lower than a potential of the bit-line electrode, the memory cell, the bit-line, and the word-line are part of a tile comprising a plurality of memory cells, bit-lines, and word-lines, the tile has a first linear dimension that extends in a direction that is parallel to a lengthwise dimension of the bit-line and a second linear dimension that extends in a direction that is parallel to a lengthwise dimension of the word-line; the first linear dimension is greater than the second linear dimension; and the tile comprises a same number of bit-lines and word-lines.
17. The apparatus of claim 16 , further comprising: current-limiting circuitry of a selection module coupled to the word-line electrode, the current-limiting circuitry to facilitate a selection operation of the memory cell by the selection module.
18. The apparatus of claim 17 , wherein the current-limiting circuitry comprises a transistor gate that is to limit a current of the word-line electrode to a maximum current level.
19. The apparatus of claim 16 , further comprising: write circuitry coupled to the word-line electrode, the write circuitry to perform a write operation of the memory cell.
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December 22, 2014
March 22, 2016
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