A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device, comprising: at least one semiconductor chip with a first main surface, a second main surface and at least one side surface; an electrically conducting layer arranged on at least one region of the second main surface and on at least one region of the at least one side surface, wherein at least one region of the electrically conductive layer forms a coplanar surface with the first main surface of the at least one semiconductor chip; and a molding compound disposed on the electrically conducting layer.
2. The semiconductor device of claim 1 , wherein the electrically conducting layer is formed as a grid structure.
3. The semiconductor device of claim 1 , further comprising a wiring layer overlying the first main surface of the at least one semiconductor chip and the at least one region of the electrically conductive layer.
4. The semiconductor device of claim 3 , wherein the wiring layer comprises: a first dielectric layer overlying the first main surface of the at least one semiconductor chip and having an opening therein that exposes at least a portion of the at least one region of the electrically conductive layer; and an electrically conductive interconnect layer overlying the first dielectric layer and making electrical contact down to the at least one region of the electrically conductive layer through the opening.
5. The semiconductor device of claim 4 , wherein the wiring layer further comprises a second dielectric layer overlying the electrically conductive interconnect layer.
6. The semiconductor device of claim 1 , wherein the electrically conducting layer is formed as a closed layer which covers interfaces between the at least one semiconductor chip and the molding compound.
7. A semiconductor device, comprising: at least one semiconductor chip with a first main surface and a second main surface; an electrically insulating material arranged on at least one region of the second main surface, wherein at least one region of the electrically insulating material forms a coplanar surface with the first main surface of the at least one semiconductor chip; an electrically conducting layer arranged on at least one region of the electrically insulating layer; and a molding compound arranged on at least one region of the electrically conducting layer.
8. The semiconductor device of claim 7 , wherein the electrically conducting layer forms an electromagnetic shielding for the at least one semiconductor chip.
9. The semiconductor device of claim 7 , wherein the first main surface of the at least one semiconductor chip comprises an active structure.
10. The semiconductor device of claim 7 , wherein the second main surface of the at least one semiconductor chip is a rear side.
11. The semiconductor device of claim 7 , wherein a wiring structure is disposed on at least one region of the first main surface of the semiconductor chip.
12. The semiconductor device of claim 11 , wherein the electrically conductive layer is electrically coupled to the wiring structure.
13. The semiconductor device of claim 11 , wherein the wiring structure comprises: a dielectric layer overlying the first main surface of the at least one semiconductor chip and having one or more shielding vias and one or more contact vias therein; and wherein the one or more shielding vias extend through the electrically insulating material and expose one or more contact regions associated with at least one semiconductor chip, and wherein the one or more contact vias expose one or more contact regions associated with the at least one semiconductor chip.
14. The semiconductor device of claim 13 , further comprising a patterned metallization layer overlying the dielectric layer and forming metallization contacts to the electrically conductive layer and metallization contacts to the contact regions.
15. The semiconductor device of claim 7 , wherein at least one region of the electrically conductive layer is exposed from the molding compound.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 14, 2014
March 22, 2016
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