A semiconductor structure is arranged on an integrated circuit, the integrated circuit includes a seal ring arranged at outer periphery of the integrated circuit, a metal ring arranged at an inner side of the seal ring and a power bus arranged at a side of the metal ring. The semiconductor structure includes a first P type electrode area, a second P type electrode area and a first N type electrode area. The first P type electrode area is formed at a position on a P well corresponding to the seal ring, and coupled to the seal ring. The second P type electrode area is formed at a position on the P well corresponding to the metal ring, and coupled to the metal ring. The first N type electrode area is formed at a position corresponding to the power bus, and coupled to the power bus.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor structure for electrostatic discharge protection, arranged on an integrated circuit, the integrated circuit comprising a seal ring arranged at outer periphery of the integrated circuit, a metal ring arranged at an inner side of the seal ring, and a power bus arranged at a side of the metal ring, the semiconductor structure comprising: a first P type electrode area formed at a position on a P well corresponding to the seal ring, and coupled to the seal ring; a second P type electrode area formed at a position on the P well corresponding to the metal ring, and coupled to the metal ring; and a first N type electrode area formed at a position corresponding to the power bus, and coupled to the power bus; wherein the seal ring and the metal ring are coupled to ground, and the power bus is coupled to a voltage source.
2. The semiconductor structure of claim 1 , wherein the first P type electrode area, the second P type electrode area and the first N type electrode area are separated by a plurality of insulating areas.
3. The semiconductor structure of claim 1 , wherein the plurality of insulating areas are field oxide (FOX) areas.
4. The semiconductor structure of claim 1 , wherein the first N type electrode area is partially formed on the P well and an N well.
5. The semiconductor structure of claim 1 , wherein the first N type electrode area is formed on the P well.
6. The semiconductor structure of claim 5 , wherein the integrated circuit further comprises an N well coupled to the voltage source.
7. The semiconductor structure of claim 5 , wherein the P well is formed on a P type substrate, the integrated circuit further comprises an N type buried layer arranged between the P well and the P type substrate.
8. The semiconductor structure of claim 1 , wherein the power bus is arranged between the seal ring and the metal ring.
9. The semiconductor structure of claim 8 , wherein the first N type electrode area is extended outward to form an N type doping area, and doping concentration of the N type doping area is lower than doping concentration of the first N type electrode area.
10. The semiconductor structure of claim 1 further comprising: a second N type electrode area formed at a position on the P well corresponding to the seal ring, and coupled to the seal ring; and a third N type electrode area formed at a position corresponding to the metal ring, and coupled to the metal ring.
11. The semiconductor structure of claim 10 , wherein the second N type electrode area is closer to the first N type electrode area than the first P type electrode area, and the third N type electrode area is closer to the first N type electrode area than the second P type electrode area.
12. The semiconductor structure of claim 1 , wherein the integrated circuit further comprises a plurality of coupling units for coupling the seal ring and the metal ring.
13. The semiconductor structure of claim 1 , wherein the seal ring, the metal ring and the power bus are arranged at a same layer.
14. A semiconductor structure for electrostatic discharge protection, arranged on an integrated circuit, the integrated circuit comprising a seal ring arranged at outer periphery of the integrated circuit, a metal ring arranged at an inner side of the seal ring, and a power bus arranged at a side of the metal ring, the semiconductor structure comprising: a first N type electrode area formed at a position on an N well corresponding to the seal ring, and coupled to the seal ring; a second N type electrode area formed at a position on the N well corresponding to the power bus, and coupled to the power bus; and a first P type electrode area formed at a position corresponding to the metal ring, and coupled to the metal ring; wherein the seal ring and the power bus are coupled to a voltage source, and the metal ring is coupled to ground.
15. The semiconductor structure of claim 14 , wherein the first N type electrode area, the second N type electrode area and the first P type electrode area are separated by a plurality of insulating areas.
16. The semiconductor structure of claim 15 , wherein the plurality of insulating areas are field oxide (FOX) areas.
17. The semiconductor structure of claim 14 further comprising a P well, wherein the first P type electrode area is partially formed on the P well.
18. The semiconductor structure of claim 14 , wherein the metal ring is arranged between the seal ring and the power bus.
19. The semiconductor structure of claim 18 , wherein the integrated circuit further comprises a metal layer arranged above the seal ring, the metal ring and the power bus, for coupling the seal ring and the power bus.
20. A semiconductor structure for electrostatic discharge protection, arranged on an integrated circuit, the integrated circuit comprising a seal ring arranged at outer periphery of the integrated circuit, a metal ring arranged at an inner side of the seal ring, and a power bus arranged at a side of the metal ring, the semiconductor structure comprising: a first N type electrode area formed at a position on an P well corresponding to the seal ring, and coupled to the seal ring; a second N type electrode area formed at a position on the P well corresponding to the power bus, and coupled to the power bus; and a first P type electrode area formed at a position on the P well corresponding to the metal ring, and coupled to the metal ring; wherein the seal ring and the power bus are coupled to a voltage source, and the metal ring is coupled to ground.
21. The semiconductor structure of claim 20 , wherein the first N type electrode area, the second N type electrode area and the first P type electrode area are separated by a plurality of insulating areas.
22. The semiconductor structure of claim 21 , wherein the plurality of insulating areas are field oxide (FOX) areas.
23. The semiconductor structure of claim 20 further comprising: a first N well, wherein a center part of the first N type electrode area is formed on the first N well, and a peripheral part of the first N type electrode area is formed on the P well; and a second N well, wherein a center part of the second N type electrode area is formed on the second N well, and a peripheral part of the second N type electrode area is formed on the P well.
24. The semiconductor structure of claim 20 further comprising: a first N type doping area, formed between the first N type electrode area and the P well, wherein doping concentration of the first N type doping area is lower than doping concentration of the first N type electrode area; and a second N type doping area, formed between the second N type electrode area and the P well, wherein doping concentration of the second N type doping area is lower than doping concentration of the second N type electrode area.
25. The semiconductor structure of claim 20 , wherein the metal ring is arranged between the seal ring and the power bus.
26. The semiconductor structure of claim 25 , wherein the integrated circuit further comprises a metal layer arranged above the seal ring, the metal ring and the power bus, for coupling the seal ring and the power bus.
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October 12, 2014
March 22, 2016
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