Image capturing device

1. An image capturing device comprising: a pixel circuit region in which a plurality of pixel circuits are arranged in a matrix; a peripheral circuit region that is located on a periphery of the pixel circuit region and in which a peripheral circuit is arranged; and an intermediate region that is located between the pixel circuit region and the peripheral circuit region and that forms a boundary with the pixel circuit region and the peripheral circuit region, wherein the pixel circuit region, the peripheral circuit region, and the intermediate region are provided with a semiconductor layer, a first wiring layer located on the semiconductor layer, and a second wiring layer located away from the semiconductor layer relative to the first wiring layer, and the pixel circuits and the peripheral circuit are connected via one of at least the first wiring layer and the second wiring layer in the intermediate region, and wherein an area occupancy of the one wiring layer in the intermediate region relative to a total area of the intermediate region is between 0.5 times and 1.5 times an area occupancy of the one wiring layer in the pixel circuit region relative to a total area of the pixel circuit region.

2. The image capturing device according to claim 1 , wherein the intermediate region is provided with a contact for supplying reference potential of the pixel circuits.

3. The image capturing device according to claim 2 , wherein the one wiring layer includes a conductive line that extends across the pixel circuit region from the intermediate region and that supplies the reference potential.

4. The image capturing device according to claim 2 , wherein the other one of the first wiring layer and the second wiring layer includes a conductive line that extends across the pixel circuit region from the intermediate region and that supplies the reference potential.

5. The image capturing device according to claim 1 , wherein the one wiring layer is the second wiring layer.

6. The image capturing device according to claim 1 , wherein an area occupancy of the second wiring layer in the intermediate region relative to the total area of the intermediate region is lower than an area occupancy of the first wiring layer in the intermediate region relative to the total area of the intermediate region.

7. The image capturing device according to claim 1 , wherein an area occupancy of the first wiring layer in the intermediate region relative to the total area of the intermediate region is between 0.7 times and 1.3 times an area occupancy of the first wiring layer in the pixel circuit region relative to the total area of the pixel circuit region.

8. The image capturing device according to claim 1 , wherein, in the intermediate region, a conductive line constituted by the first wiring layer and a conductive line constituted by the second wiring layer intersect with each other at multiple locations.

9. The image capturing device according to claim 1 , wherein a zone that includes at least one of the plurality of pixel circuits in the pixel circuit region is defined as a first zone, and a zone in the intermediate region that has a contour that is the same as a contour of the first zone is defined as a second zone, and wherein the one wiring layer is located in the first zone and the second zone, and a matching rate between a pattern of the one wiring layer in the second zone and a pattern of the one wiring layer in the first zone is 50% or higher.

10. The image capturing device according to claim 9 , wherein the pixel circuit region, the peripheral circuit region, and the intermediate region are provided with an insulation film that is located between the first wiring layer and the semiconductor layer and through which an electrically conductive member connected to the semiconductor layer extends, wherein the pixel circuit region, the peripheral circuit region, and the intermediate region are provided with an electrode layer located between the insulation film and the semiconductor layer, and the electrode layer constitutes electrodes of the pixel circuits in the pixel circuit region and constitutes an electrode of the peripheral circuit in the peripheral circuit region, and wherein the electrode layer is located in the first zone and the second zone, and a matching rate between a pattern of the electrode layer in the second zone and a pattern of the electrode layer in the first zone is 50% or higher.

11. The image capturing device according to claim 1 , wherein the area occupancy of the one wiring layer located in the intermediate region relative to the total area of the intermediate region is lower than an area occupancy of the one wiring layer in the peripheral circuit region relative to a total area of the peripheral circuit region.

12. The image capturing device according to claim 1 , wherein the pixel circuit region, the peripheral circuit region, and the intermediate region are provided with an insulation film that is located between the first wiring layer and the semiconductor layer and through which an electrically conductive member connected to the semiconductor layer extends, wherein the pixel circuit region, the peripheral circuit region, and the intermediate region are provided with an electrode layer located between the insulation film and the semiconductor layer, and the electrode layer constitutes electrodes of the pixel circuits in the pixel circuit region and constitutes an electrode of the peripheral circuit in the peripheral circuit region, and wherein an area occupancy of the electrode layer located in the intermediate region relative to the total area of the intermediate region is between 0.5 times and 1.5 times an area occupancy of the electrode layer located in the pixel circuit region relative to the total area of the pixel circuit region.

13. The image capturing device according to claim 12 , wherein an area occupancy of the electrically conductive member located in the intermediate region relative to the total area of the intermediate region is between 0.5 times and 1.5 times an area occupancy of the electrically conductive member located in the pixel circuit region relative to the total area of the pixel circuit region.

14. The image capturing device according to claim 12 , wherein the pixel circuit region and the intermediate region are provided with a dielectric member that extends through an insulation layer located on the semiconductor layer, and wherein an area occupancy of the dielectric member located in the intermediate region relative to the total area of the intermediate region is between 0.5 times and 1.5 times an area occupancy of the dielectric member located in the pixel circuit region relative to the total area of the pixel circuit region.

15. The image capturing device according to claim 14 , wherein the insulation layer is located between the first wiring layer and the second wiring layer, and a dielectric constant of the dielectric member is higher than a dielectric constant of the insulation layer.

16. The image capturing device according to claim 15 , wherein the pixel circuit region, the peripheral circuit region, and the intermediate region are provided with an element isolation layer located between the insulation film and the semiconductor layer, and wherein an area occupancy of the element isolation layer in the intermediate region is between 0.5 times and 1.5 times an area occupancy of the element isolation layer in the pixel circuit region.

17. The image capturing device according to claim 1 , wherein the pixel circuit region, the peripheral circuit region, and the intermediate region are provided with an insulation film that is located between the one wiring layer and the semiconductor layer and through which an electrically conductive member connected to the semiconductor layer extends, wherein the pixel circuit region, the peripheral circuit region, and the intermediate region are provided with an element isolation layer located between the insulation film and the semiconductor layer, and wherein an area occupancy of the element isolation layer located in the intermediate region relative to the total area of the intermediate region is between 0.5 times and 1.5 times an area occupancy of the element isolation layer located in the pixel circuit region relative to the total area of the pixel circuit region.

18. The image capturing device according to claim 1 , wherein the pixel circuit region, the peripheral circuit region, and the intermediate region are provided with an insulation film that is located between the one wiring layer and the semiconductor layer and through which an electrically conductive member connected to the semiconductor layer extends, wherein the pixel circuit region, the peripheral circuit region, and the intermediate region are provided with an element isolation layer located between the insulation film and the semiconductor layer, wherein a zone that includes at least one of the plurality of pixel circuits in the pixel circuit region is defined as a first zone, and a zone in the intermediate region that has a contour that is the same as a contour of the first zone is defined as a second zone, and wherein the element isolation layer is located in the first zone and the second zone, and a matching rate between a pattern of the element isolation layer in the intermediate region and a pattern of the element isolation layer in the pixel circuit region is 50% or higher.

19. The image capturing device according to claim 1 , wherein a distance between the pixel circuit region and the peripheral circuit region with the intermediate region interposed therebetween is between 10 μm and 100 μm.

20. An image capturing device comprising: a pixel circuit region in which a plurality of pixel circuits are arranged in a matrix; a peripheral circuit region that is located on a periphery of the pixel circuit region and in which a peripheral circuit is arranged; and an intermediate region that is located between the pixel circuit region and the peripheral circuit region and that forms a boundary with the pixel circuit region and the peripheral circuit region, wherein the pixel circuit region, the peripheral circuit region, and the intermediate region are provided with an insulation film that is located on a semiconductor layer and through which an electrically conductive member connected to the semiconductor layer extends, wherein the pixel circuit region, the peripheral circuit region, and the intermediate region are provided with an electrode layer located between the insulation film and the semiconductor layer, and the electrode layer constitutes electrodes of the pixel circuits in the pixel circuit region, constitutes an electrode of the peripheral circuit in the peripheral circuit region, and constitutes a dummy electrode in the intermediate region, wherein the pixel circuit region and the intermediate region are provided with contacts for supplying reference potential to the semiconductor layer via the electrically conductive member, and the number of contacts in the pixel circuit region is one-third or smaller of the number of pixels provided in the pixel circuit region, wherein a ratio of the number of contacts to the number of dummy electrodes in the intermediate region is larger than a ratio of the number of contacts to the number of electrodes in the pixel circuit region, and wherein an area occupancy of the electrode layer in the intermediate region is between 0.5 times and 1.5 times an area occupancy of the electrode layer in the pixel circuit region.