Systems and methods for optimizing a memory rail voltage are disclosed. The system may comprise a plurality of sensor cells, each sensor cell comprising at least one bitcell replica having a predefined data retention voltage higher than a data retention voltage of a similar memory bit cell. The sensor cells may be configured to provide an output based on a sensor rail voltage higher than the predefined data retention voltage. The system may further comprise a controller operably coupled to a power management circuit and configured to adjust the memory rail and the sensor rail voltages. The controller may be further configured to compare an expected value to the sensor indication. The controller may decrease the sensor rail voltage and the memory rail voltage based on the indication until a sensor indicates a bitcell replica has failed, indicating an optimum memory rail voltage has been reached.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus for optimizing a memory rail voltage supplied to a plurality of memory bitcells, the memory bitcells of the plurality of memory bitcells configured to retain a memory value when a memory rail voltage is above a first data retention voltage, comprising: a plurality of sensor cells, each sensor cell comprising at least one bitcell replica having a predefined data retention voltage and configured to provide an output based on a sensor rail voltage, each sensor cell configured to provide a sensor indication comprising the output of the at least one bitcell replica; a power management circuit operably coupled to the plurality of sensor cells and configured to provide the memory rail voltage and the sensor rail voltage; and a controller operably coupled to the power management circuit and to the plurality of sensor cells, the controller configured to: compare an expected value to the sensor indication of one or more of the plurality of sensor cells; and decrease the sensor rail voltage and the memory rail voltage when the sensor indication matches the expected value.
2. The apparatus of claim 1 , wherein the controller is further configured to decrease the memory rail voltage and the sensor rail voltage until at least one sensor indication does not match the expected value.
3. The apparatus of claim 1 , wherein the controller is further configured to bypass a sensor cell of the plurality of sensor cells when the sensor indication does not match the expected value, indicating a bitcell replica failure; and monitor the remaining sensor cells of the plurality of sensor cells for additional failures.
4. The apparatus of claim 3 , wherein the controller is further configured to increase the memory rail voltage and the sensor rail voltage when the output of the plurality of sensor cells does not match the expected value.
5. The apparatus of claim 1 , wherein the controller is further configured to adjust the memory rail voltage to a level equal to a maximum data retention voltage of a highest data retention voltage of the plurality of memory bitcells.
6. The apparatus of claim 1 , wherein the sensor indication comprises a combination of a plurality of outputs of a plurality of bitcell replicas, the sensor indication being sensitive to a single output.
7. The apparatus of claim 1 , wherein the output is indicative of an ability of the at least one bitcell replica to retain a binary memory value.
8. The apparatus of claim 1 , wherein the predefined data retention voltage is higher than the first data retention voltage, such that the at least one bitcell replica will fail at a higher memory rail voltage than the memory bitcells.
9. The apparatus of claim 1 , wherein the at least one bitcell replica is further configured to have a data retention sensitivity to at least one of process and temperature, the data retention sensitivity further being similar to that of the memory bitcells.
10. The apparatus of claim 1 , wherein the memory rail and the sensor rail have a common power supply circuit controlled by the controller.
11. The apparatus of claim 1 , wherein the controller is further configured to transmit a system warning when the memory rail voltage is at a nominal supply voltage and the output of the sensor cell and the expected value do not match.
12. The apparatus of claim 1 , wherein the expected value is indicative of a value of an output of a bitcell replica that is receiving a sensor rail voltage greater than the predefined data retention voltage.
13. A method for optimizing a memory rail voltage supplied to a plurality of memory bitcells, the plurality of memory bitcells configured to retain a memory value when a memory rail voltage is above a first data retention voltage, the method comprising: providing a memory rail voltage to the plurality of memory bitcells and a sensor rail voltage to a sensor cell, the sensor cell comprising at least one bitcell replica having a predefined data retention voltage, the sensor cell being configured to provide a sensor indication, the sensor indication indicating an output of the at least one bitcell replica, the output based on the sensor rail voltage; receiving a sensor indication from the sensor cell; comparing an expected value to the sensor indication; and decreasing the sensor rail voltage and the memory rail voltage when the sensor indication matches the expected value.
14. The method of claim 13 further comprising decreasing the memory rail voltage and the sensor rail voltage until at least one sensor indication does not match the expected value.
15. The method of claim 13 further comprising: bypassing the sensor cell when the sensor indication does not match the expected value, indicating a bitcell replica failure; and monitoring one or more other sensor cells of a plurality of sensor cells for additional failures.
16. The method of claim 15 further comprising increasing the memory rail voltage and the sensor rail voltage when the sensor indication does not match the expected value.
17. The method of claim 13 further comprising adjusting the memory rail voltage to a level equal to a maximum data retention voltage of a highest data retention voltage of the plurality of memory bitcells.
18. The method of claim 13 further comprising concatenating a plurality of outputs of the at least one bitcell replica within each sensor cell, the sensor indication being sensitive to a single output, wherein the at least one bitcell replica comprises two or more bitcell replicas.
19. The method of claim 13 , wherein the output is indicative of an ability of the at least one bitcell replica to retain a binary memory value.
20. The method of claim 13 , wherein the predefined data retention voltage is higher than the first data retention voltage, such that the at least one bitcell replica will fail at a higher memory rail voltage than the plurality of memory bitcells.
21. An apparatus for optimizing a memory rail voltage supplied to a plurality of memory bitcells, the memory bitcells configured to retain a memory value when a memory rail voltage is above a first data retention voltage, comprising: a plurality of means for sensing an ability of one or more memory bitcells of the plurality of memory bitcells to retain a memory value, each means for sensing configured to provide an indication based on a sensor rail voltage; a means for managing power operably coupled to the plurality of means for sensing and configured to provide the memory rail voltage and the sensor rail voltage; and a means for controlling operably coupled to the means for managing power and to the plurality of means for sensing, the means for controlling configured to: compare an expected value to the indication of one or more of the plurality of means for sensing, and decrease the sensor rail voltage and the memory rail voltage in voltage increments until one of the outputs of the plurality of sensing means does not match the expected value.
22. The apparatus of claim 21 , wherein the means for sensing comprises a plurality of sensor cells, each sensor cell comprising at least one bitcell replica having a predefined data retention voltage and configured to provide an output based on the sensor rail voltage, and wherein the indication comprises the output of the at least one bitcell replica.
23. The apparatus of claim 21 , wherein the means for managing power comprises a power management circuit and the means for receiving and the means for comparing comprise at least one controller.
24. The apparatus of claim 21 , wherein the means for controlling is further configured to: bypass at least one sensing means of the plurality of sensing means when the indication does not match the expected value; and monitor the remaining sensing means.
25. The apparatus of claim 21 , wherein the means for controlling is further configured to increase the memory rail voltage and the sensor rail voltage when the output of the plurality of means for sensing does not match the expected value.
26. An apparatus for optimizing a memory rail voltage comprising: a plurality of sensor cells, each sensor cell comprising at least one bitcell replica, each bitcell replica having a predefined data retention voltage higher than a data retention voltage of a similar memory bitcell, each sensor cell configured to provide a sensor indication comprising an output of the at least one bitcell replica, the output being based on a sensor rail voltage; a sensor rail power management circuit operably connected to each sensor cell and configured to supply the sensor rail voltage; a memory rail power management circuit operably connected to each memory bitcell of a plurality of memory bitcells and configured to supply the memory rail voltage; and a controller operably connected to the sensor rail and memory rail power management circuits and configured to: compare each of the sensor indications to an expected value, decrease the memory rail voltage and sensor rail voltage in voltage increments until one sensor indication does not match the expected value, indicating that at least one bitcell replica has failed, bypass one or more failed sensor cells, monitor the bitcells that have not failed, and increase the memory rail voltage and sensor rail voltage by at least one increment if additional sensor cells fail and if the rail voltages are less than a maximum nominal value (Vddnom).
27. The apparatus of claim 26 , wherein the controller is further configured to adjust the memory rail voltage to a level equal to a maximum data retention voltage of a highest data retention voltage of the plurality of memory bitcells.
28. The apparatus of claim 26 , wherein the sensor indication comprises a combination of a plurality of outputs of a plurality of bitcell replicas, the sensor indication being sensitive to a single output.
29. The apparatus of claim 26 , wherein the at least one bitcell replica is further configured to have a data retention sensitivity to at least one of process and temperature, the data retention sensitivity further being similar to that of the memory bitcells.
30. The apparatus of claim 26 , wherein the controller is further configured to transmit a system warning when the memory rail voltage is at a nominal supply voltage and the output of the sensor cell and the expected value do not match.
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February 2, 2015
March 29, 2016
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