A mechanism is provided for accessing data in a hybrid hardware managed cache in front of flash memory enabling load/store byte addressability to flash memory. A determination is made as to whether a real address associated with the effective address associated with a request resides in a page table. Responsive to the real address existing in the page table, responsive to the real address referring to a flash page, and, responsive to the flash page failing to reside in the hybrid hardware managed cache, a load-through fault is issued that allows the faulting processor executing the request to execute other work while the flash page is brought into the hybrid hardware managed cache. The operation is then issued to the new hybrid hardware managed cache real address.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method, in a data processing system, for accessing data in a hybrid hardware managed cache, the method comprising: responsive to receiving a request to perform an operation at an effective address, determining whether a real address associated with the effective address resides in a page table; responsive to the real address existing in the page table, determining whether the real address refers to a flash page or a normal page; responsive to the real address referring to a flash page, determining whether the flash page resides in a portion of system memory dedicated as the hybrid hardware managed cache; responsive to the flash page failing to reside in the hybrid hardware managed cache: issuing a load-through fault thereby allowing a faulting processor executing the request to execute other work while the flash page is brought into the hybrid hardware managed cache; assigning a new hybrid hardware managed cache real address in the hybrid hardware managed cache; and moving the flash page from a flash memory to the hybrid hardware managed cache; and issuing the operation to the new hybrid hardware managed cache real address.
2. The method of claim 1 , further comprising: installing the new hybrid hardware managed cache real address in a translation lookaside buffer (TLB); and installing the new hybrid hardware managed cache real address in an effective to real address table (ERAT).
3. The method of claim 1 , further comprising: responsive to the flash page residing in the hybrid hardware managed cache, installing the real address associated with the flash page in a translation lookaside buffer (TLB); installing the real address associated with the flash page in an effective to real address table (ERAT); and reissuing the operation to the real address associated with the flash page.
4. The method of claim 1 , further comprising: responsive to the load-through fault being issued, performing a first context switch out of the faulting thread; initiating a timer set to a latency of a flash memory; dispatching one or more other threads; responsive to the time expiring, performing a second context switch; and redispatching the original faulting thread.
5. The method of claim 4 , wherein the timer duration is selected based on whether the request causing the load-through fault is a load or a store.
6. The method of claim 1 , further comprising: responsive to the load-through fault being issued, performing a first context switch out faulting thread; dispatching one or more other threads; responsive to a load-through complete fault being issued, performing a second context switch; and redispatching the original faulting thread.
7. The method of claim 1 , wherein the system memory is a dynamic random-access memory (DRAM).
8. The method of claim 1 , wherein the flash memory is a flash solid state drive (SSD), a flash dual inline memory module (DIMM), or a flash Peripheral Component Interconnect (PCI) card.
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June 12, 2014
April 12, 2016
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