In an embodiment of the invention, a method of performing a byte-rotate-merge on computer hardware is discussed. Byte-rotating is performed on first and second source operands and are byte-rotated by first and second rotation constants respectively. The first byte-rotate output and the second byte-rotate output are merged. Bytes from the first byte-rotate output are output to a byte-rotate-merge output when control bits from a byte-mask are logical ones. Bytes from the second byte-rotate output are output to a byte-rotate-merge output when control bits from the byte-mask are logical zeros.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of performing a deposit-field instruction on computer hardware the method comprising: receiving a source argument and a background argument; receiving a destination position argument, a source position argument and a length argument; rotating the source argument by a ROT argument wherein the ROT argument is equal to the destination position argument minus the source position argument resulting in an byte-rotate output; applying the source position argument to a first thermometer decoder wherein an output of the first thermometer enables bits from the source position argument and higher; applying the destination position argument plus the length argument to a second thermometer wherein an output of the second thermometer enables bits from the destination position argument plus the length argument and down; applying the output of the first thermometer and the output of the second thermometer to a AND gate wherein an output of the AND controls a multiplexer; wherein a result of the deposit-field instruction is completed in a single clock cycle.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 12, 2013
April 12, 2016
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