An operating method is for operating a memory controller which controls a non-volatile memory device. The non-volatile memory device includes a plurality of memory cells arranged in a direction perpendicular to a substrate. The operating method includes erasing the plurality of memory cells, reading memory cells connected with a first word line using a first word line voltage to search string address information corresponding to memory cells being at an off state, and programming memory cells corresponding to the string address information to a particular program state based on the string address information to store mapping information.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An operating method of a memory controller which controls an operation of a non-volatile memory device, the non-volatile memory device including a plurality of memory cells arranged in a direction perpendicular to a substrate, the operating method comprising: erasing the plurality of memory cells; reading memory cells connected with a first word line using a first word line voltage to search string address information corresponding to memory cells being at an off state; and programming memory cells corresponding to the string address information to a particular program state based on the string address information to store mapping information.
2. The operating method of claim 1 , wherein the mapping information and data of memory cells not corresponding to the string address information are encoded, and the encoded data is provided to the non-volatile memory device.
3. The operating method of claim 1 , wherein the mapping information is stored at the non-volatile memory device.
4. The operating method of claim 1 , wherein when all the memory cells are at an erase state, the first word line voltage is a threshold voltage for determining an erase state.
5. The operating method of claim 1 , wherein the first word line voltage is higher than a threshold voltage corresponding to a program state of the non-volatile memory device.
6. The operating method of claim 1 , wherein the particular program state has a threshold voltage higher than an uppermost program state of the non-volatile memory device.
7. The operating method of claim 1 , wherein the string address information is stored at one of the non-volatile memory device and the memory controller.
8. The operating method of claim 1 , wherein the memory cells are configured as NAND flash memory cell strings.
9. An operating method of a non-volatile memory device which comprises at least one cell string including a plurality of memory cells, a string select transistor and a ground select transistor arranged in a direction perpendicular to a substrate, the operating method comprising: erasing the plurality of memory cells; reading memory cells connected with a first word line using a first word line voltage; searching string address information corresponding to memory cells being at an off state; and storing mapping information indicating that memory cells corresponding to the string address information are programmed to a particular program state.
10. The operating method of claim 9 , further comprising: programming an encoding result of the mapping information and an encoding result of data of memory cells not corresponding to the searched address, at a memory cell array.
11. The operating method of claim 9 , wherein the string select transistor is not electrically connected with a bit line.
12. The operating method of claim 9 , wherein the ground select transistor is not electrically connected with the substrate.
13. The operating method of claim 9 , wherein memory cells being at an off state are included in a string where a channel for electrically connecting the memory cells is not formed.
14. The operating method of claim 9 , wherein the program state has a threshold voltage higher than an uppermost program state of the non-volatile memory device.
15. The operating method of claim 9 , wherein the non-volatile memory device is a NAND flash memory.
16. An operating method of a memory system, the memory system including a memory controller and a non-volatile memory, the non-volatile memory including a three-dimensional memory cell array comprising cell strings extending perpendicularly relative to a substrate and word lines intersecting the cell strings, the method comprising: identifying first string addresses corresponding to off-state cells among memory cells connected to a word line, and remaining second string addresses not corresponding to off-state cells among the memory cells connected to the word line; mapping original data corresponding to the first string addresses to first program states; and encoding the mapped data and data corresponding to the second string addresses.
17. The operating method of claim 16 , further comprising storing the mapped data prior to encoding the mapped data.
18. The operating method of claim 16 , further comprising providing the non-volatile memory with the encoded data.
19. The operating method of claim 16 , wherein identifying the first string addresses includes: erasing the memory cells; reading the memory cells connected to the word line using a first word line voltage; searching string address information corresponding to memory cells which are read as being in an off state.
20. The operating method of claim 16 , wherein the memory cells are configured as NAND flash memory cell strings.
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November 27, 2013
April 19, 2016
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