Patentable/Patents/US-9318474
US-9318474

Thermally enhanced wafer level fan-out POP package

PublishedApril 19, 2016
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

In some embodiments, a semiconductor device package assembly may include a first substrate. The semiconductor device package assembly may include a first die electrically connected to the first substrate such that the first die is directly bonded to the first substrate. The semiconductor device package assembly may include a second substrate directly bonded to a surface of the first die. The semiconductor device package assembly may include an electronic memory module. The electronic memory module may be directly bonded to the second substrate. The semiconductor device package assembly may include a thermally conductive material directly applied to the electronic memory module. The semiconductor device package assembly may include a heat spreader directly bonded to the thermally conductive material. The heat spreader may function to transfer heat from the first die and the electronic memory module through the heat spreader from the first side to the second side.

Patent Claims
15 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A semiconductor device package assembly, comprising: a first substrate including a first surface, a second surface substantially opposite of the first surface, and a first set of electrical conductors coupled to the first surface configured to electrically connect the semiconductor device package assembly; a first die electrically connected to the second surface of the first substrate using a second set of electrical conductors such that the first die is directly bonded to the first substrate, wherein the second set of electrical conductors are configured to electrically connect to at least some of the first set of electrical conductors; a third set of electrical conductors coupled to the second surface of the first substrate, wherein the third set of electrical conductors are configured to electrically connect to at least some of the first set of electrical conductors; a second substrate comprising a first surface and a second surface substantially opposite of the first surface, wherein the first surface is directly bonded to a surface of the first die opposite the second set of electrical conductors; an electronic memory module comprising a third substrate comprising a first surface and a second surface substantially opposite of the first surface, wherein the first surface is directly bonded to the second surface of the second substrate using a fourth set of electrical conductors; wherein the electronic memory module comprises at least two second die electrically connected to the second surface of the third substrate in a fan out configuration using a fifth set of electrical conductors such that the at east two second die are directly bonded to the third substrate; a thermally conductive material directly applied to a second surface of the electronic memory module; and a heat spreader comprising a first side and a second side substantially opposite the first side, wherein the first side is directly bonded to the thermally conductive material, and wherein the heat spreader is configured to transfer heat from the first die and the electronic memory module through the heat spreader from the first side to the second side, wherein at least a portion of the heat transferred from the first die is conveyed through the second substrate and the electronic memory module to the second side of the heat spreader.

2

2. The assembly of claim 1 , wherein the electronic memory module comprises: at least one second die electrically connected to the second surface of the third substrate using a fifth set of electrical conductors such that the second die is directly bonded to the third substrate.

3

3. The assembly of claim 1 , wherein substantially no air gap is present between the electronic memory module and the second substrate.

4

4. The assembly of claim 1 , wherein, during use, heat travels from the first die to the heat spreader without traversing an air gap.

5

5. The assembly of claim 1 , wherein a Z height of the assembly is less than 1 mm.

6

6. The assembly of claim 1 , wherein the first die is connected to the second surface of the first substrate using a flip chip configuration.

7

7. A semiconductor device package assembly, comprising: a first substrate including a first surface, a second surface substantially opposite of the first surface, and a first set of electrical conductors coupled to the first surface configured to electrically connect the semiconductor device package assembly; a first die electrically connected to the second surface of the first substrate using a second set of electrical conductors such that the first die is directly bonded to the first substrate, wherein the second set of electrical conductors are configured to electrically connect to at least some of the first set of electrical conductors; a third set of electrical conductors coupled to the second surface of the first substrate, wherein the third set of electrical conductors are configured to electrically connect to at least some of the first set of electrical conductors; an electronic memory module comprising a third substrate comprising a first surface and a second surface substantially opposite of the first surface, wherein the first surface is directly bonded to a surface of the first die opposite the second set of electrical conductors; wherein the electronic memory module comprises at least one second die electrically connected to the second surface of the third substrate using a fifth set of electrical conductors such that the second die is directly bonded to the third substrate; a thermally conductive material directly applied to the second surface of the electronic memory module; and a heat spreader comprising a first side and a second side substantially opposite the first side, wherein the first side is directly bonded to the thermally conductive material, and wherein the heat spreader is configured to transfer heat from the first die and the electronic memory module through the heat spreader from the first side to the second side, wherein, during use, heat is transferred from the first die to the heat spreader without traversing an air gap.

8

8. The assembly of claim 7 , wherein the electronic memory module comprises: at least two second die electrically connected to the second surface of the third substrate in a fan out configuration using a fifth set of electrical conductors such that the at least two second die are directly bonded to the third substrate.

9

9. The assembly of claim 7 , wherein a Z height of the assembly is less than 1 mm.

10

10. The assembly of claim 7 , wherein the first die is connected to the second surface of the first substrate using a flip chip configuration.

11

11. A method for forming a semiconductor device package assembly, comprising: forming a first substrate comprising a first surface, a second surface substantially opposite of the first surface, and a first set of electrical conductors coupled to the first surface; electrically connecting the semiconductor device package assembly using the first set of electrical conductors; directly bonding a first die to the second surface of the first substrate using a second set of electrical conductors such that the first die is electrically connected to the first substrate; electrically connecting the second set of electrical conductors to at least some of the first set of electrical conductors; electrically connecting a third set of electrical conductors coupled to the second surface of the first substrate to at least some of the first set of electrical conductors; directly bonding a first surface of a second substrate to a surface of the first die opposite the second set of electrical conductors, wherein the second substrate comprises a second surface substantially opposite of the first surface; directly bonding a first surface of a third substrate forming at least a portion of an electronic memory module to the second surface of the second substrate using a fourth set of electrical conductors, wherein the third substrate comprises a second surface substantially opposite of the first surface; directly bonding at least two second die forming at least a portion of the electronic memory module to the second surface of the third substrate in a fan out configuration using a fifth set of electrical conductors such that the at least two second die are electrically connected to the third substrate; applying a thermally conductive material directly to a second surface of the electronic memory module; directly bonding a first side of a heat spreader to the thermally conductive material, wherein the heat spreader comprises a second side substantially opposite the first side; and transferring heat from the first die and the electronic memory module through the heat spreader from the first side to the second side of the heat spreader, wherein, during use, heat is transferred from the first die to the heat spreader without traversing an air gap.

12

12. The method of claim 11 , wherein the electronic memory module comprises: directly bonding a second die to the second surface of the third substrate using a fifth set of electrical conductors such that the second die is electrically connected to the third substrate.

13

13. The method of claim 11 , wherein substantially no air gap is present between the electronic memory module and the second substrate.

14

14. The method of claim 11 , wherein a Z height of the assembly is less than 1 mm.

15

15. The method of claim 11 , wherein the first die is connected to the second surface of the first substrate using a flip chip configuration.

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Patent Metadata

Filing Date

February 27, 2014

Publication Date

April 19, 2016

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Cite as: Patentable. “Thermally enhanced wafer level fan-out POP package” (US-9318474). https://patentable.app/patents/US-9318474

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