An image coding device includes a first block encoder and a second block encoder. The first block encoder compresses input pixel values including first and second input pixel values in a block. The first input pixel value is located at a first position of the block, and the second input pixel value is located at a second position of the block. The second block encoder compresses the input pixel values by the unit block. The first and second block encoders compare the input pixel values based on different methods of compression. The first block encoder outputs the first input pixel value as a first compressed pixel value, and compresses the second input pixel value to a second compressed pixel value.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An image coding device, comprising: a first block encoder to compress a plurality of input pixel values including first and second input pixel values in a unit of a block, the first input pixel value provided at a head of the block and the second input pixel value following the first input pixel value within the block, wherein the first block encoder includes a first encoder to output the first input pixel value as a first compressed pixel value and to compress the second input pixel value to a second compressed pixel value, and wherein the second compressed pixel value has fewer bits than the first input pixel value.
2. An image coding device, comprising: a first block encoder to compress a plurality of input pixel values including first and second input pixel values in a unit of a block, the first input pixel value provided at a head of the block and the second input pixel value following the first input pixel value within the block, wherein the first block encoder includes a second encoder adapted to compress the first input pixel value to a first compressed pixel value, wherein a first encoder is to compress the second input pixel value to a second compressed pixel value, and the second compression pixel value has fewer bits than the first compressed pixel value.
3. The device as claimed in claim 2 , wherein the first encoder is to quantize a difference between the second input pixel value and a reference pixel value.
4. The device as claimed in claim 3 , wherein the reference pixel value includes a de-compressed pixel value obtained by de-compressing the first compressed pixel value.
5. The device as claimed in claim 2 , wherein the first encoder is to directly quantize the second input pixel value.
6. The device as claimed in claim 2 , further comprising: a second block encoder to compress the input pixel values by the unit of the block in a manner different from the first block encoder; and a first multiplexer to compare an error between a first de-compressed pixel value and the input pixel values with an error between a second de-compressed pixel value and the input pixel values, the first multiplexer to select and output a compressed pixel value from one of the first or second block encoders that provides a predetermined error, wherein the first de-compressed pixel value is compressed and de-compressed through the first block encoder, and wherein the second de-compressed pixel value is compressed and de-compressed through the second block encoder.
7. The device as claimed in claim 2 , wherein the first block encoder includes: a plurality of first encoders to compress the second input pixel value in different ways, and to output the compressed results as second compressed pixel values; and a second multiplexer to calculate errors between second de-compressed pixel values and the second input pixel values, to compare the errors, and to select and output a second compressed pixel value output from one of the first encoders providing a predetermined error, wherein the de-compressed pixel values are to be generated by de-compressing the second compressed pixel values.
8. The device as claimed in claim 3 , wherein: the input pixel values include a third input pixel value, and the second block encoder includes: a plurality of third encoders to compress the third input pixel value in different ways, and to output the compressed results as third compression pixel values, a third multiplexer to calculate errors between third de-compressed pixel values and the third input pixel values, to compare the errors, and to select and output a third compressed pixel value output from one of the third encoders providing a predetermined error, third de-compressed pixel values are generated by de-compressing the third compression pixel values from the third encoders.
9. A method for coding a plurality of input pixel values in a unit of a block, the method comprising: outputting a first input pixel value as a first compressed pixel value; and compressing a second input pixel value to a second compressed pixel value, wherein second compressed pixel value has fewer bits than the first compressed pixel value and wherein the first input pixel value is at a head of the block and the second input pixel value follows the first input pixel value within the block.
10. A method for coding a plurality of input pixel values in a unit of a block, the method comprising: compressing a first input pixel value to a first compressed pixel value; and compressing a second input pixel value to a second compressed pixel value, wherein the first input pixel value is provided ahead of the second input pixel value in the block and wherein the second compressed pixel value has fewer bits than the first compressed pixel value.
11. An image coding device, comprising: a first block encoder to compress input pixel values including first and second input pixel values in a block, the first input pixel value at a first position of the block and the second input pixel value at a second position of the block; and a second block encoder to compress the input pixel values by the unit block, wherein the first and second block encoders are to compare the input pixel values based on different methods of compression, and wherein the first block encoder is to output the first input pixel value as a first compressed pixel value and to compress the second input pixel value to a second compressed pixel value.
12. The device as claimed in claim 11 , wherein the second compressed pixel value has fewer bits than the first input pixel value.
13. The device as claimed in claim 11 , further comprising: a first multiplexer to compare an error between a first de-compressed pixel value and the input pixel values with an error between a second de-compressed pixel value and the input pixel values, wherein the first multiplexer is to select and output a compressed pixel value from one of the first or second block encoders that provides a predetermined error.
14. The device as claimed in claim 13 , wherein: the first de-compressed pixel value is to be compressed and de-compressed through the first block encoder, and the second de-compressed pixel value is to be compressed and de-compressed through the second block encoder.
15. The device as claimed in claim 11 , wherein the first block encoder is to quantize a difference between the second input pixel value and a reference pixel value.
16. The device as claimed in claim 15 , wherein the reference pixel value includes a de-compressed pixel value obtained by de-compressing the first compressed pixel value.
17. The device as claimed in claim 11 , wherein the first block encoder is to directly quantize the second input pixel value.
18. The device as claimed in claim 11 , wherein the first block encoder includes: a plurality of first encoders to compress the second input pixel value in different ways, and to output the compressed results as second compressed pixel values; and a second multiplexer to calculate errors between second de-compressed pixel values and the second input pixel values, to compare the errors, and to select and output a second compressed pixel value output from one of the first encoders providing a predetermined error.
19. The device as claimed in claim 18 , wherein the de-compressed pixel values are to be generated by de-compressing the second compressed pixel values.
20. The device as claimed in claim 11 , wherein: the first position is at a head position of the block, and the second position is after the first position within the block.
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September 5, 2014
April 19, 2016
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