Patentable/Patents/US-9349590
US-9349590

Method for manufacturing nitride semiconductor layer

PublishedMay 24, 2016
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

According to one embodiment, a method for manufacturing a nitride semiconductor layer is disclosed. The method can include forming a first lower layer on a major surface of a substrate and forming a first upper layer on the first lower layer. The first lower layer has a first lattice spacing along a first axis parallel to the major surface. The first upper layer has a second lattice spacing along the first axis larger than the first lattice spacing. At least a part of the first upper layer has compressive strain. A ratio of a difference between the first and second lattice spacing to the first lattice spacing is not less than 0.005 and not more than 0.019. A growth rate of the first upper layer in a direction parallel to the major surface is larger than that in a direction perpendicular to the major surface.

Patent Claims
20 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A method for manufacturing a nitride semiconductor layer, comprising: forming a first lower layer of a nitride semiconductor on a major surface of a substrate and forming a first upper layer of a nitride semiconductor on the first lower layer to form a first stacked body including the first lower layer and the first upper layer, the first lower layer having a first lattice spacing along a first axis parallel to the major surface, the first upper layer having a second lattice spacing along the first axis larger than the first lattice spacing, at least a part of the first upper layer having a first compressive strain along the major surface, an absolute value of a ratio of a difference between the second lattice spacing and the first lattice spacing to the first lattice spacing being not less than 0.005 and not more than 0.019, and the forming the first upper layer including making a growth rate of the first upper layer in a direction parallel to the major surface larger than a growth rate of the first upper layer in a direction perpendicular to the major surface, and forming the first upper layer while applying the first compressive strain on the first upper layer, the first compressive strain being based on the difference between the second lattice spacing and the first lattice spacing, wherein the second lattice spacing of the first upper layer after formation of the first stacked body has a value between an unstrained lattice constant of the first upper layer and an unstrained lattice constant of a first base layer located between the first lower layer and the substrate.

2

2. The method according to claim 1 , wherein a ratio of a number of atoms of a group-V element supplied for a unit time to a number of atoms of a group-III element supplied for the unit time in the forming the first upper layer is not less than 2000 and not more than 8000.

3

3. The method according to claim 1 , wherein a ratio of a flow rate of an ammonia gas to a flow rate of a total sum of a supply gas in the forming the first upper layer is not less than 0.2 and not more than 0.5.

4

4. The method according to claim 1 , wherein a thickness of the first upper layer is not less than 250 nanometers.

5

5. The method according to claim 1 , wherein the forming the first stacked body includes the first base layer of a nitride semiconductor on the major surface before the forming the first lower layer, and the first base layer has a lattice spacing along the first axis smaller than the first lattice spacing.

6

6. The method according to claim 5 , wherein the first base layer is made of AlN, the first lower layer is made of Al x1 Ga 1-x1 N (0<x 1 <1), and the first upper layer is made of GaN.

7

7. The method according to claim 6 , wherein the Al composition ratio x 1 in the first lower layer is not less than 0.1 and not more than 0.9.

8

8. The method according to claim 6 , wherein a thickness of the first lower layer is not less than 100 nanometers and not more than 500 nanometers.

9

9. The method according to claim 1 , wherein the substrate is a silicon substrate.

10

10. The method according to claim 1 , further comprising forming a second lower layer of a nitride semiconductor on the first stacked body and forming a second upper layer of a nitride semiconductor on the second lower layer to form a second stacked body including the second lower layer and the second upper layer, the second lower having a third lattice spacing along the first axis, the second upper layer having a fourth lattice spacing along the first axis larger than the third lattice spacing, at least a part of the second upper layer having a second compressive strain along the major surface, an absolute value of a ratio of a difference between the fourth lattice spacing and the third lattice spacing to the third lattice spacing being not less than 0.005 and not more than 0.019, and the forming the second upper layer including making a growth rate of the second upper layer in the direction parallel to the major surface larger than a growth rate of the second upper layer in the direction perpendicular to the major surface, and forming the second upper layer while applying the second compressive strain based on the difference between the fourth lattice spacing and the third lattice spacing on the second upper layer.

11

11. The method according to claim 10 , wherein the forming the second stacked body includes forming a second base layer of a nitride semiconductor on the first stacked body before the forming the second lower layer, and the second base layer has a lattice spacing along the first axis smaller than the third lattice spacing.

12

12. The method according to claim 11 , wherein the second base layer is made of AlN, the second lower layer is made of Al x2 Ga 1-x2 N (0<x 2 <1), and the second upper layer is made of GaN.

13

13. The method according to claim 12 , wherein a growth temperature of the second base layer is lower than a growth temperature of the second lower layer and lower than a growth temperature of the second upper layer.

14

14. The method according to claim 12 , wherein a growth temperature of the second base layer is not less than 500° C. and not more than 1050° C.

15

15. The method according to claim 12 , wherein a thickness of the second lower layer is not less than 5 nanometers and not more than 100 nanometers.

16

16. The method according to claim 11 , wherein a thickness of the second upper layer is thicker than a thickness of the first upper layer.

17

17. The method according to claim 11 , wherein the forming the second base layer includes forming the second base layer while applying a tensile stress on the second base layer.

18

18. The method according to claim 1 , further comprising: forming an intermediate layer of GaN between the major surface and the first stacked body; and forming a first base layer of Al y1 Ga 1-y1 N (0<y 1 ≦1) between the intermediate layer and the first lower layer, the first lower layer being made of Al x1 Ga 1-x1 N (0<x 1 <1, x 1 <y 1 ), and the Al composition ratio x 1 in the first lower layer being not more than a ratio of an absolute value of a difference between a lattice spacing along an axis equivalent to the first axis of unstrained GaN and a lattice spacing along the first axis in the first base layer to an absolute value of a difference between the lattice spacing along the axis equivalent to the first axis of unstrained GaN and a lattice spacing along the axis equivalent to the first axis of the unstrained Al y1 Ga 1-y1 N (0<y 1 ≦1).

19

19. The method according to claim 18 , wherein the forming the first lower layer includes forming the first lower layer while applying a second compressive strain on the first lower layer, and the second compressive strain along the major surface.

20

20. The method according to claim 1 , further comprising: forming a second base layer of Al y2 Ga 1-y2 N (0<y 2 ≦1) on the first stacked body, forming a second lower layer of Al x2 Ga 1-x2 N (0<x 2 <1, x 2 <y 2 ) on the second base layer, and forming a second upper layer of GaN on the second lower layer to form a second stacked body including the second base layer, the second lower layer and the second upper layer, the second lower layer having a third lattice spacing along the first axis larger than a lattice spacing along the first axis of the second base layer, the second upper layer having a fourth lattice spacing along the first axis larger than the third lattice spacing, at least a part of the second upper layer having compressive strain along the major surface, an absolute value of a ratio of a difference between the fourth lattice spacing and the third lattice spacing to the third lattice spacing being not less than 0.005 and not more than 0.019, the forming the second upper layer including making a growth rate of the second upper layer in the direction parallel to the major surface larger than a growth rate of the second upper layer in the direction perpendicular to the major surface, and forming the second upper layer while applying compressive strain along the major surface based on the difference between the fourth lattice spacing and the third lattice spacing on the second upper layer, the first lower layer being made of Al x1 Ga 1-x1 N (0<x 1 <1); the first upper layer being made of GaN; and the Al composition ratio x 2 in the second lower layer being not more than a ratio of an absolute value of a difference between a lattice spacing along an axis equivalent to the first axis of unstrained GaN and a lattice spacing along the first axis in the second base layer to an absolute value of a difference between the lattice spacing along the axis equivalent to the first axis of unstrained GaN and a lattice spacing along the axis equivalent to the first axis of the unstrained Al y2 Ga 1-y2 N (0<y 2 ≦1).

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Patent Metadata

Filing Date

September 5, 2012

Publication Date

May 24, 2016

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Cite as: Patentable. “Method for manufacturing nitride semiconductor layer” (US-9349590). https://patentable.app/patents/US-9349590

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