A circuit configured to detect the conduction of a first body diode and a second body diode of the first and second synchronous rectification transistors is provided. The circuit includes a low-pass filter configured to generate a filtered voltage by receiving a detection voltage based on a drain voltage of the first synchronous rectification transistor and low-pass filtering the received drain voltage, a first comparator configured to compare whether the filtered voltage is higher than the detection voltage, and a second comparator configured to compare whether the detection voltage is higher than the filtered voltage. A time point of ending a first synchronous rectification conduction interval of the first body diode and a time point of a second synchronous rectification conduction interval of the second body diode are determined, according to outputs from the first and second comparators.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A conduction detecting circuit configured to detect conduction of a first body diode connected in parallel to a first synchronous rectification transistor which is connected to one end of a first winding, and a second body diode connected in parallel to a second synchronous rectification transistor which is connected to one end of a second winding, respectively, the circuit comprising: a low-pass filter configured to generate filtered voltage by filtering a detection voltage based on a drain voltage of the first synchronous rectification transistor; a first comparator configured to detect a time point at which the detection voltage decreases to be lower than the filtered voltage by at least a first reference voltage; and a second comparator configured to detect a time point at which the detection voltage increases to be higher than the filtered voltage by at least a second reference voltage, wherein a time point of ending a first synchronous rectification conduction interval of the first body diode and a time point of ending a second synchronous rectification conduction interval of the second body diode are detected by the conduction detecting circuit according to outputs from the first and second comparators.
2. The conduction detection circuit of claim 1 , wherein the time point of ending the first synchronous rectification conduction interval is determined based on the output from the second comparator when the detection voltage is higher than the filtered voltage by at least the second reference voltage.
3. The conduction detection circuit of claim 1 , wherein the time point of ending the second synchronous rectification conduction interval is determined based on the output from the first comparator when the detection voltage is lower than the filtered voltage by at least the first reference voltage.
4. The conduction detection circuit of claim 1 , further comprising a third comparator configured to determine whether the detection voltage is higher than a predetermined reference voltage.
5. The conduction detection circuit of claim 1 , further comprising an SR flip-flop configured to generate an enable level of output signal according to the output from the second comparator, and generate an enable level of an inverted output signal according to the output from the first comparator.
6. The conduction detection circuit of claim 5 , further comprising a first logic operator configured to generate a first OFF signal, indicating the time point of ending the first synchronous rectification conduction interval according to the output signal from the SR flip-flop, when the detection voltage is higher than a predetermined reference voltage.
7. The conduction detection circuit of claim 6 , further comprising a second logic operator configured to generate a second OFF signal, indicating the time point of ending the second synchronous rectification conduction interval according to the inverted output signal from the SR flip-flop and an inverted signal of the first OFF signal.
8. The conduction detection circuit of claim 1 , wherein the low-pass filter comprises: a resistor comprising an end configured to receive the detection voltage; and a capacitor connected to the resistor, wherein the filtered voltage is a voltage from where the resistor connects to the capacitor.
9. A rectification switch control circuit configured to control a switching operation of a first synchronous rectification transistor and a second synchronous rectification transistor connected in parallel to a first body diode and a second body diode, respectively, which conduct according to a resonance current under control of a switching operation of a first switch and a second switch, the rectification switch control circuit comprising: a conduction detection circuit configured to detect a time point of ending a first synchronous rectification conduction interval of the first body diode and a time point of ending a second synchronous rectification conduction interval of the second body diode based on a detection voltage corresponding to a drain voltage of the first synchronous rectification transistor and a filtered voltage generated by a low-pass filter; and an edge trigger configured to generate a first edge signal at a turn-on time of the first switch and generate a second edge signal at a turn-on time of the second switch, wherein a time point of beginning the first synchronous rectification conduction interval is in synchronization with the first edge signal, and a time point of beginning the second synchronous rectification conduction interval is in synchronization with the second edge signal.
10. The rectification switch control circuit of claim 9 , wherein the control circuit turns on the first synchronous rectification transistor when the first switch turns on and the detection voltage is rapidly falling, and turns off the first synchronous rectification transistor when a predetermined ON period elapses from the turn-on time, and sets the predetermined ON period based on a result of subtracting a predetermined period from the first synchronous rectification conduction interval in an immediately-preceding switching period of the first synchronous rectification transistor.
11. The rectification switch control circuit of claim 9 , wherein the control circuit turns on the second synchronous rectification transistor when the second switch turns on and the detection voltage is rapidly rising, and turns off the second synchronous rectification transistor when a predetermined ON period elapses from the turn-on time, and sets the predetermined ON period based on a result of subtracting a predetermined period from the second synchronous rectification conduction interval in an immediately-preceding switching period of the second synchronous rectification transistor.
12. The rectification switch control circuit of claim 9 , wherein the conduction detection circuit determines a time point of ending the second synchronous rectification conduction interval when the detection voltage is lower than the filtered voltage by at least a first reference voltage, and determines a time point of ending the first synchronous rectification conduction interval when the detection voltage is higher than the filtered voltage by at least a second reference voltage.
13. The rectification switch control circuit of claim 12 , wherein the conduction detection circuit comprises: a first comparator configured to determine if the detection voltage is lower than the filtered voltage by at least the first reference voltage; a second comparator configured to determine if the detection voltage is higher than the filtered voltage by at least the second reference voltage; an SR flip-flop configured to generate an enable level of output signal according to an output from the second comparator and generates an enable level of inverted output signal according to an output from the first comparator and to generate a first OFF signal, indicating a time point of ending the first synchronous rectification conduction interval according to an output signal from the SR flip-flop, and to generate a second OFF signal, indicating a time point of ending the second synchronous rectification conduction interval according to an inverted signal of the first OFF signal and an inverted output signal from the SR flip-flop.
14. The rectification switch control circuit of claim 9 , wherein the edge trigger in synchronization with the time point of ending the first synchronous rectification conduction interval generates a third edge signal, and the edge trigger in synchronization with the time point of ending the second synchronous rectification conduction interval generates a fourth edge signal.
15. The rectification switch control circuit of claim 14 , further comprising: a first SR flip-flop configured to generate an enable level of first synchronous rectification conduction signal according to the first edge signal and generate a disable level of first synchronous rectification conduction signal according to the third edge signal; and a second SR flip-flop configured to generate an enable level of second synchronous rectification conduction signal according to the second edge signal and generate a disable level of second synchronous rectification conduction signal according to the fourth edge signal.
16. The rectification switch control circuit of claim 15 , wherein the control circuit counts the first and second synchronous rectification conduction intervals using the first and second synchronous rectification conduction signals, respectively.
17. The rectification switch control circuit of claim 9 , wherein the edge trigger comprises: a delayer configured to delay an input signal for a predetermined delay time before outputting the same; an inverter configured to invert an output from the delayer; and an AND gate configured to perform the AND operation of the input signal and an output from the inverter, wherein the input signal is a gate voltage of the first switch or a gate voltage of the second switch.
18. A power supply, comprising: a first switch; a second switch connected to one end of the first switch; a primary side winding connected to one end of the first switch; a first body diode connected to one end of a first winding of a secondary side; a second body diode connected to one end of a second winding having a second end is connected to a second end of the first winding of the secondary side; a first synchronous rectification transistor connected in parallel to the first body diode; and a second synchronous rectification transistor connected in parallel to the second body diode, wherein a time point of ending the first synchronous rectification conduction interval of the first body diode and a time point of ending the second synchronous rectification conduction interval of the second body diode are detected using a detection voltage corresponding to the drain voltage of the first synchronous rectification transistor and a filtered voltage generated by a low-pass filter.
19. The power supply of claim 18 , wherein a time point of beginning the first synchronous rectification conduction interval is in synchronization with the turn-on time of the first switch, and a time point of beginning the second synchronous rectification conduction interval is in synchronization with the turn-on time of the second switch.
20. The power supply of claim 18 , wherein a time point of ending the second synchronous rectification conduction interval is determined when the detection voltage is lower than the filtered voltage by at least a first reference voltage, and a time point of ending the first synchronous rectification conduction interval is determined when the detection voltage is higher than the filtered voltage by at least a second reference voltage.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 13, 2014
May 24, 2016
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.