This semiconductor memory device comprises a memory cell array that includes: a plurality of first lines; a plurality of second lines intersecting the plurality of first lines; a plurality of memory cells each disposed at an intersection of the plurality of first lines and the plurality of second lines and including a variable resistance element; and a select transistor respectively connected to an end of the plurality of first lines. The select transistor includes a gate electrode, a gate insulating film, and a conductive layer. Moreover, one end of that conductive layer is connected to the end of the first line, and a non-linear resistance layer configured from a non-linear material is connected between the first line and the conductive layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor memory device, comprising: a memory cell array including: a first conductive line, the first conductive line extending in a first direction; second conductive lines, the second conductive lines extending in a second direction intersecting the first direction; a variable resistance element, the variable resistance element being disposed at an intersection of the first conductive line and the second conductive lines and disposed between the first conductive line and the second conductive lines; a third conductive line, the third conductive line extending in a third direction intersecting the first direction; and a select transistor, the select transistor including a gate electrode, a gate insulating film, and a semiconductor layer, the semiconductor layer disposed between an end of the first conductive line at a side in the first direction and the third conductive line; and a non-linear resistance layer disposed between the end of the first conductive line at the side in the first direction and the semiconductor layer, the non-linear resistance layer being configured from a non-linear material.
2. The semiconductor memory device according to claim 1 , wherein the non-linear resistance layer is formed of a material identical to that of the variable resistance element.
3. The semiconductor memory device according to claim 1 , wherein the non-linear resistance layer is formed of an oxide of any of Hf, Al, Ti, Ni, W, and Ta.
4. The semiconductor memory device according to claim 1 , wherein the non-linear resistance layer is formed of a material different from a material of the variable resistance element.
5. The semiconductor memory device according to claim 4 , wherein the variable resistance element is formed of HfOx, and the non-linear resistance layer is formed of TaOx.
6. The semiconductor memory device according to claim 1 , further comprising: a control circuit, wherein the control circuit is configured to, before a read operation, execute a first operation for changing the non-linear resistance layer from a first resistance state to a second resistance state.
7. The semiconductor memory device according to claim 6 , wherein the control circuit is configured to, after finishing the read operation, execute a second operation for changing the non-linear resistance layer from the second resistance state to the first resistance state.
8. A semiconductor memory device, comprising: a memory cell array including: a first conductive line, the first conductive line extending in a first direction; second conductive lines, the second conductive line extending in a second direction intersecting the first direction; a variable resistance element, the variable resistance element being disposed at an intersection of the first conductive line and the second conductive lines and disposed between the first conductive line and the second conductive lines; a third conductive line, the third conductive line extending in a third direction intersecting the first direction; and a select transistor, the select transistor including a gate electrode, a gate insulating film, and a conductive layer, the conductive layer disposed between an end of the first conductive line at a side in the first direction and the third conductive line; and a non-linear resistance layer disposed between the end of the first conductive line at the side in the first direction and the conductive layer, the non-linear resistance layer having a non-linear voltage-current characteristic stronger than that of the first conductive line.
9. The semiconductor memory device according to claim 8 , wherein the non-linear resistance layer is formed of a material identical to that of the variable resistance element.
10. The semiconductor memory device according to claim 8 , wherein the non-linear resistance layer is formed of an oxide of any of Hf, Al, Ti, Ni, W, and Ta.
11. The semiconductor memory device according to claim 8 , wherein the non-linear resistance layer is formed of a material different from a material of the variable resistance element.
12. The semiconductor memory device according to claim 11 , wherein the variable resistance element is formed of HfOx, and the non-linear resistance layer is formed of TaOx.
13. The semiconductor memory device according to claim 8 , further comprising: a control circuit, wherein the control circuit is configured to, before a read operation, execute a first operation for changing the non-linear resistance layer from a first resistance state to a second resistance state.
14. The semiconductor memory device according to claim 13 , wherein the control circuit is configured to, after finishing the read operation, execute a second operation for changing the non-linear resistance layer from the second resistance state to the first resistance state.
15. The semiconductor memory device according to claim 1 , further comprising: a substrate, wherein the first conductive line is disposed above the substrate, and the first direction is perpendicular to a surface of the substrate.
16. The semiconductor memory device according to claim 8 , further comprising: a substrate, wherein the first conductive line is disposed above the substrate, and the first direction is perpendicular to a surface of the substrate.
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February 12, 2014
June 14, 2016
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