One embodiment relates to a method for determining a latency of a network port. Read and write pointers for a FIFO are sampled at the same time. An average difference between a plurality of samples of the read and write pointers is determined. Another embodiment relates to an apparatus for providing timestamps to packets at a network port. Registers sample read and write pointers of a FIFO using a sampling clock. Logic circuitry determines an average difference between the read and write pointers, and timestamping circuitry receives the average difference and inserts timestamps into packets. Other embodiments and features are also disclosed.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for determining a latency of a network port, the method comprising: generating a sampling clock at a sampling frequency; sampling a read pointer for a first-in-first-out (FIFO) buffer using an edge of the sampling clock; sampling a write pointer for the FIFO buffer using the edge of the sampling clock; and determining an average difference between the read and write pointers.
2. The method of claim 1 , wherein a greatest common divisor between a clock period of the sampling clock and the clock period of a read clock of the FIFO buffer is less than one-half of the clock period of the read clock, and wherein a greatest common divisor between the clock period of the sampling clock and the clock period of a write clock of the FIFO buffer is less than one-half of the clock period of the write clock.
3. The method of claim 1 , wherein a greatest common divisor between the clock period of the sampling clock and the clock period of a read clock of the FIFO buffer is less than one-fourth of the clock period of the read clock, and wherein a greatest common divisor between the clock period of the sampling clock and the clock period of a write clock of the FIFO buffer is less than one-fourth of the clock period of the write clock.
4. The method of claim 3 , wherein the sampling clock is slower than the read and write clocks.
5. The method of claim 1 , wherein read and write clocks of the FIFO buffer have a same speed.
6. The method of claim 1 , wherein the average difference is used in generating timestamps.
7. The method of claim 1 , wherein the average difference is determined to a precision that corresponds to a lag time precision of 200 picoseconds or less.
8. An apparatus for determining a latency of a network port, the apparatus comprising: a sample clock generation circuit for generating a sampling clock; a first register for sampling a read pointer for a first-in first-out (FIFO) buffer of the network port using the sampling clock; a second register for sampling a write pointer for the FIFO buffer using the sampling clock; and logic circuitry for determining an average difference between the read pointer and the write pointer.
9. The apparatus of claim 8 , wherein a greatest common divisor between the clock period of the sampling clock and the clock period of the read clock is less than one-half of the clock period of the read clock, and wherein a greatest common divisor between the clock period of the sampling clock and the clock period of the write clock is less than one-half of the clock period of the write clock.
10. The apparatus of claim 8 , wherein a greatest common divisor between the clock period of the sampling clock and the clock period of the read clock is less than one-fourth of the clock period of the read clock, and wherein a greatest common divisor between the clock period of the sampling clock and the clock period of the write clock is less than one-fourth of the clock period of the write clock.
11. The apparatus of claim 10 , wherein the sampling clock is slower than the read and write clocks.
12. The apparatus of claim 8 , wherein the read and write clocks have a same speed.
13. The apparatus of claim 8 , wherein the average difference is determined to a precision that corresponds to a lag time precision of 200 picoseconds or less.
14. The apparatus of claim 8 , wherein the logic circuitry for determining the average difference is configured in programmable circuitry.
15. A serial interface circuit comprising: a transmission first-in first-out (FIFO) buffer for receiving a parallel data signal in a first clock domain and outputting the parallel data signal in a second clock domain; a transmission gearbox for converting the parallel data signal from a first width to a second width; a serializer for converting the parallel data signal having the second width in bits to a serial data signal; a first register for sampling a read pointer for the transmission FIFO buffer using a sampling clock; a second register for sampling a write pointer for the transmission FIFO buffer using the sampling clock; and logic circuitry for determining an average difference between the read pointer and the write pointer.
16. The serial interface circuit of claim 15 , wherein a greatest common divisor between the clock period of the sampling clock and the clock period of the read clock is less than one-half of the clock period of the read clock, and wherein a greatest common divisor between the clock period of the sampling clock and the clock period of the write clock is less than one-half of the clock period of the write clock.
17. The serial interface circuit of claim 15 , wherein the sampling clock is slower than the read and write clocks.
18. The serial interface circuit of claim 15 , wherein the read and write clocks have a same speed.
19. The serial interface circuit of claim 15 , wherein the average difference is determined to a precision that corresponds to a lag time precision of 200 picoseconds or less.
20. A serial interface circuit comprising: a deserializer for receiving a serial data signal and converting the serial data signal into a parallel data signal; a receiver gearbox for converting the parallel data signal from a first width to a second width; a receiver first-in first-out (FIFO) buffer for receiving the parallel data signal in a first clock domain and outputting the parallel data signal in a second clock domain; a first register for sampling a read pointer for the receiver FIFO buffer using a sampling clock; a second register for sampling a write pointer for the receiver FIFO buffer using the sampling clock; and logic circuitry for determining an average difference between the read pointer and the write pointer.
21. The serial interface circuit of claim 20 , wherein a greatest common divisor between the clock period of the sampling clock and the clock period of the read clock is less than one-half of the clock period of the read clock, and wherein a greatest common divisor between the clock period of the sampling clock and the clock period of the write clock is less than one-half of the clock period of the write clock.
22. The serial interface circuit of claim 20 , wherein the sampling clock is slower than the read and write clocks.
23. The serial interface circuit of claim 20 , wherein the read and write clocks have a same speed.
24. The serial interface circuit of claim 20 , wherein the average difference is determined to a precision that corresponds to a lag time precision of 200 picoseconds or less.
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June 10, 2015
June 14, 2016
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