The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace) in a multicore SoC. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters. The two consecutive slots assigned per cache line access are always in the same direction for maximum access rate.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A Multicore Shared Memory Controller (MSMC) comprising: a plurality of slave interfaces, each operable for connection to a corresponding one of a plurality of central processing units for receiving access requests; a plurality of master interfaces operable for connection to an external memory interface (EMIF); datapath module connected to each slave interface and to each master interface, said datapath module including an arbitration unit operable to arbitrate access of a center processing unit to a memory by unifying all accesses to a particular master interface before access requests are arbitrated.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 23, 2013
June 21, 2016
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