Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for semiconductor fabrication, comprising: forming a material stack of at least one semiconductor layer and at least one dielectric layer on a bulk semiconductor substrate including a well region; forming a pocket in the well region directly under the at least one dielectric layer by ion implanting dopant through the material stack, wherein the pocket and the well region provide a p-n junction; and creating defects at the p-n junction to reduce junction leakage.
2. The method as recited in claim 1 , wherein creating defects includes creating defects as part of a same implantation used to form the pocket.
3. The method as recited in claim 1 , wherein creating defects includes using a same mask used to form the pocket to apply a separate implantation.
4. The method as recited in claim 1 , wherein creating defects includes performing a blanket implantation over the substrate.
5. The method as recited in claim 1 , wherein the defects include end-of-range implant defects.
6. The method as recited in claim 1 , wherein the defects include impurities that generate mid-gap states.
7. The method as recited in claim 1 , wherein creating defects includes creating defects inside a depletion region associated with the p-n junction.
8. The method as recited in claim 1 , wherein the well region is formed by implanting p-type or n-type dopants applied at an implant dose ranging from 10 13 /cm 2 to 10 16 /cm 2 with an implant energy ranging from 2 KeV to 200 KeV.
9. The method as recited in claim 8 , wherein the pocket is formed by impanting p-type or n-type dopants applied at an implant dose ranging from 10 13 /cm 2 to 10 16 /cm 2 with an implant energy ranging from 5 KeV to 100 KeV.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 10, 2015
June 21, 2016
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