A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A device comprising: a substrate comprising a first surface and a second surface under the first surface; a conductive feature extending from the first surface into the substrate, wherein the conductive feature comprises: a conductive pad extending over the first surface of the substrate, wherein the conductive pad comprises a substantially planar top surface opposite the substrate; and a conductive bump contacting the conductive pad, wherein the conductive bump comprises a non-planar top surface over the substantially planar top surface, and wherein the conductive bump and the conductive pad are formed of a same material.
2. The device of claim 1 , wherein the non-planar top surface of the conductive bump is rounded.
3. The device of claim 1 , wherein no interface is formed between the conductive bump and the conductive pad.
4. The device of claim 1 , wherein the conductive bump is aligned with a portion of the conductive feature in the substrate.
5. The device of claim 1 , wherein the substantially planar top surface is aligned to a portion of the substrate encircling the conductive feature.
6. The device of claim 1 further comprising an under-bump metallurgy (UBM) over the conductive bump and the conductive pad, wherein the UBM comprises a first portion over and in contact with the non-planar top surface of the conductive bump, and a second portion over and in contact with the substantially planar top surface of the conductive pad.
7. The device of claim 1 further comprising a solder region over the conductive pad and the conductive bump, wherein the solder region comprises a first bottom surface that is not planar, and a second bottom surface that is substantially planar.
8. The device of claim 1 further comprising a passivation layer, wherein the passivation layer comprises portions covering edge portions of the conductive pad.
9. The device of claim 8 further comprising a stress buffer layer over the passivation layer, wherein the stress buffer layer comprises portions covering the edge portions of the conductive pad.
10. The device of claim 9 , further comprising a solder region over the conductive pad and the conductive bump, wherein the stress buffer layer is underlying and aligned to the solder region, and wherein the stress buffer layer does not extend beyond the solder region.
11. A device comprising: a semiconductor substrate comprising a first surface and a second surface over the first surface; a through-via extending through the semiconductor substrate from the first surface to the second surface; and a metal connector over the second surface of the semiconductor substrate and the through-via, wherein a surface of the metal connector opposite the semiconductor substrate comprises: a substantially planar portion; and a non-planar portion extending over the substantially planar portion, wherein the substantially planar portion extends laterally past the non-planar portion.
12. The device of claim 11 , wherein the metal connector and the through-via are formed of a same material, and wherein no visible interface is formed between the through-via and the metal connector.
13. The device of claim 11 , further comprising: a nickel-containing layer in contact with the metal connector, wherein the nickel-containing layer comprises a non-planar portion aligned to the through-via, and a planar portion not aligned to the through-via; and a solder region over the nickel-containing layer, wherein the solder region comprises a non-planar bottom surface portion aligned to the through-via, and a planar bottom surface portion not aligned to the through-via.
14. The device of claim 13 , further comprising stress buffer layer disposed between the nickel-containing layer and the metal connector.
15. The device of claim 14 , wherein the stress buffer layer is only disposed under the solder region.
16. A device comprising: a substrate comprising an integrated circuit device at a first side; a first conductive feature extending from the first side of the substrate past a second side of the substrate opposite the first side of the substrate, and wherein a portion of the first conductive feature extending past the second side of the substrate comprises: a substantially planar first surface; and a non-planar second surface connected to the substantially planar first surface; a second conductive feature over and contacting the first conductive feature; and a solder region over and contacting the second conductive feature.
17. The device of claim 16 , wherein the first and the second conductive features are formed of different materials.
18. The device of claim 16 further comprising a passivation layer covering edge portions of the first conductive feature.
19. The device of claim 18 further comprising a stress buffer layer over the passivation layer, wherein the stress buffer layer is disposed between the second conductive feature and the passivation layer.
20. The device of claim 16 , wherein the non-planar second surface of the first conductive feature is higher than the substantially planar first surface by greater than about 0.1 μm.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 28, 2015
June 21, 2016
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.