A nitride semiconductor wafer includes a silicon substrate, a stacked multilayer unit, a silicon-containing unit, and an upper layer unit. The silicon substrate has a major surface. The stacked multilayer unit is provided on the major surface. The stacked multilayer unit includes N number of buffer layers. The buffer layers include an i-th buffer layer, and an (i+1)-th buffer layer provided on the i-th buffer layer. The i-th buffer layer has an i-th lattice length Wi in a first direction parallel to the major surface. The (i+1)-th buffer layer has an (i+1)-th lattice length W(i+1) in the first direction. A relation that (W(i+1)−Wi)/Wi≦0.008 is satisfied for all the buffer layers. The silicon-containing unit is provided on the stacked multilayer unit. The upper layer unit is provided on the silicon-containing unit.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A nitride semiconductor device comprising: a silicon substrate having a major surface; a stacked multilayer unit formed on the major surface of the silicon substrate, the stacked multilayer unit including N number of buffer layers stacked in a stacking direction perpendicular to the major surface, the buffer layers including a nitride semiconductor, N being not less than two and not more than nine, the buffer layers including an i-th buffer layer (i being an integer of 1 or more and less than N), and an (i+1)-th buffer layer provided on the i-th buffer layer, the (i+1)-th buffer layer being in contact with the i-th buffer layer, the i-th buffer layer having an i-th lattice length Wi in a first direction parallel to the major surface, the (i+1)-th buffer layer having an (i+1)-th lattice length W(i+1) in the first direction, and a relation that 0.003≦(W(i+1)−Wi)/Wi≦0.008 being satisfied for all the buffer layers; a silicon-containing unit provided on the stacked multilayer unit and containing silicon, the silicon-containing unit being in contact with the stacked multilayer unit; an upper layer unit provided on the silicon-containing unit and including a nitride semiconductor wherein the upper layer unit includes an upper buffer layer provided on the silicon-containing unit and including a nitride semiconductor, and a functional layer provided on the upper buffer layer and including a nitride semiconductor, the functional layer includes an impurity-containing layer containing an impurity, and an impurity concentration in the impurity-containing layer is higher than an impurity concentration in the upper buffer layer, the upper layer unit further includes an intermediate layer provided between the upper buffer layer and the functional layer, the intermediate layer includes a first layer including a nitride semiconductor containing Al, and a second layer provided on the first layer and including a nitride semiconductor, an Al composition ratio of the second layer is lower than an Al composition of the first layer, the intermediate layer further includes a third layer including a nitride semiconductor including Al and provided between the first layer and the second layer, and an Al composition ratio of the third layer is lower than the Al composition ratio of the first layer and higher than the Al composition ratio of the second layer.
2. The device according to claim 1 , wherein one of the buffer layers has a first surface parallel to the major surface, the first surface is a c-plane, and the first direction is an a-axis direction.
3. The device according to claim 1 , wherein the buffer layers include a lower most buffer layer closest to the silicon substrate, and an upper most buffer layer closest to the silicon-containing unit, the lower most buffer layer includes Al x1 Ga 1-x1 N (0<x1≦1), the upper most buffer layer includes Al xn Ga 1-xn N (0≦xn<x1), and the i-th buffer layer provided between the lower most buffer layer and the upper most layer includes Al xi Ga 1-xi N (xn<xi<x1).
4. The device according to claim 3 , wherein an Al composition ratio in the (i+1)-th buffer layer is lower than an Al composition ratio in the i-th buffer layer.
5. The device according to claim 1 , wherein a silicon concentration in the silicon-containing unit is 6.2×10 19 atoms/cm 3 or more and 4.0×10 20 atoms/cm 3 or less.
6. The device according to claim 1 , wherein the upper buffer layer includes Al x0 Ga 1-x0 N (0≦x0<1).
7. The device according to claim 1 , wherein the functional layer includes a first semiconductor layer of a first conductivity type provided on the upper buffer layer, a light emitting layer provided on the first semiconductor layer; and a second semiconductor layer of a second conductivity type provided on the light emitting layer.
8. The device according to claim 1 , wherein the upper layer unit further includes a foundation layer, the foundation layer is provided between the upper buffer layer and the functional layer and includes a nitride semiconductor, and a concentration of an impurity included in the foundation layer is lower than a concentration of an impurity included in the functional layer.
9. A method for manufacturing a nitride semiconductor wafer, comprising: forming a stacked multilayer unit on a major surface of a silicon substrate, the stacked multilayer unit including N number of buffer layers stacked in a stacking direction perpendicular to the major surface, the stacked multilayer unit being in contact with the major surface, the buffer layers including a nitride semiconductor, N being not less than two and not more than nine, the buffer layers including an i-th buffer layer (i being an integer of 1 or more and less than N), and an (i+1)-th buffer layer provided on the i-th buffer layer, the (i+1)-th buffer layer being in contact with the i-th buffer layer, the i-th buffer layer having a i-th lattice length Wi in a first direction parallel to the major surface, the (i+1)-th buffer layer having a (i+1)-th lattice length W(i+1) in the first direction, and a relation that 0.003≦(W(i+1)−Wi)/Wi≦0.008 being satisfied for all the buffer layers; forming a silicon-containing unit containing silicon on the stacked multilayer unit, the silicon-containing unit being in contact with the stacked multilayer unit; and forming an upper layer unit including a nitride semiconductor on the silicon-containing unit, wherein the upper layer unit includes an upper buffer layer provided on the silicon-containing unit and including a nitride semiconductor, and a functional layer provided on the upper buffer layer and including a nitride semiconductor, the functional layer includes an impurity-containing layer containing an impurity, and an impurity concentration in the impurity-containing layer is higher than an impurity concentration in the upper buffer layer, the upper layer unit further includes an intermediate layer provided between the upper buffer layer and the functional layer, the intermediate layer includes a first layer including a nitride semiconductor containing Al, and a second layer provided on the first layer and including a nitride semiconductor, an Al composition ratio of the second layer is lower than an Al composition of the first layer, the intermediate layer further includes a third layer including a nitride semiconductor including Al and provided between the first layer and the second layer, and an Al composition ratio of the third layer is lower than the Al composition ratio of the first layer and higher than the Al composition ratio of the second layer.
10. The method according to claim 9 , wherein the functional layer includes: a third semiconductor layer provided on the upper buffer layer, and a fourth semiconductor layer provided on the third semiconductor layer to form a heterojunction with the third semiconductor layer, and wherein a bandgap of the fourth semiconductor layer is larger than a bandgap of the third semiconductor layer.
11. A nitride semiconductor wafer comprising: a silicon substrate having a major surface; a stacked multilayer unit provided on the major surface and including N number of buffer layers stacked in a stacking direction perpendicular to the major surface, the buffer layers including a nitride semiconductor, N being not less than two and not more than nine, the buffer layers including an i-th buffer layer (i being an integer of 1 or more and less than N), and an (i+1)-th buffer layer provided on the i-th buffer layer, the i-th buffer layer having an i-th lattice length Wi in a first direction parallel to the major surface, the (i+1)-th buffer layer having an (i+1)-th lattice length W(i+1) in the first direction, and a relation that 0.003≦(W(i+1)−Wi)/Wi≦0.008 being satisfied for all the buffer layers; a silicon-containing unit provided on the stacked multilayer unit and containing silicon; and an upper layer unit provided on the silicon-containing unit and including a nitride semiconductor, wherein: the upper layer unit includes an upper buffer layer provided on the silicon-containing unit and including a nitride semiconductor, and a functional layer provided on the upper buffer layer and including a nitride semiconductor, the functional layer includes an impurity-containing layer containing an impurity, and an impurity concentration in the impurity-containing layer is higher than an impurity concentration in the upper buffer layer, the upper layer unit further includes an intermediate layer provided between the upper buffer layer and the functional layer, the intermediate layer includes a first layer including a nitride semiconductor containing Al, and a second layer provided on the first layer and including a nitride semiconductor, an Al composition ratio of the second layer is lower than an Al composition of the first layer, the intermediate layer further includes a third layer including a nitride semiconductor including Al and provided between the first layer and the second layer, and an Al composition ratio of the third layer is lower than the Al composition ratio of the first layer and higher than the Al composition ratio of the second layer.
12. The wafer according to claim 11 , wherein one of the buffer layers has a first surface parallel to the major surface, the first surface is a c-plane, and the first direction is an a-axis direction.
13. The wafer according to claim 11 , wherein the buffer layers include a lower most buffer layer closest to the silicon substrate, and an upper most buffer layer closest to the silicon-containing unit, the lower most buffer layer includes Al x1 Ga 1-x1 N (0<x1≦1), the upper most buffer layer includes Al xn Ga 1-xn N (0≦xn<x1), and the i-th buffer layer provided between the lower most buffer layer and the upper most layer includes Al xi Ga 1-xi N (xn<xi<x1).
14. The wafer according to claim 13 , wherein an Al composition ratio in the (i+1)-th buffer layer is lower than an Al composition ratio in the i-th buffer layer.
15. The wafer according to claim 11 , wherein a silicon concentration in the silicon-containing unit is 6.2×10 19 atoms/cm 3 or more and 4.0×10 20 atoms/cm 3 or less.
16. The wafer according to claim 11 , wherein the upper buffer layer includes Al x0 Ga 1-x0 N (0≦x0<1).
17. The wafer according to claim 11 , wherein the functional layer includes a first semiconductor layer of a first conductivity type provided on the upper buffer layer, a light emitting layer provided on the first semiconductor layer, and a second semiconductor layer of a second conductivity type provided on the light emitting layer.
18. The wafer according to claim 11 , wherein the upper layer unit further includes a foundation layer, the foundation layer is provided between the upper buffer layer and the functional layer and includes a nitride semiconductor, and a concentration of an impurity included in the foundation layer is lower than a concentration of an impurity included in the functional layer.
19. The wafer according to claim 11 , wherein the functional layer includes: a third semiconductor layer provided on the upper buffer layer, and a fourth semiconductor layer provided on the third semiconductor layer to form a heterojunction with the third semiconductor layer, and a bandgap of the fourth semiconductor layer is larger than a bandgap of the third semiconductor layer.
20. The wafer according to claim 11 , wherein the stacked multilayer is in contact with the major surface, and the (i+1)-th buffer layer is in contact with the i-th buffer layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 28, 2012
July 19, 2016
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