An integrated circuit includes a first stage including first logic gates each of which performs a first logic operation on a corresponding signal among first to Nth signals and a first bit of a binary code, and a second stage including second logic gates each of which performs a second logic operation on corresponding output signals of the first logic gates and is reset based on a second bit of the binary code.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated circuit, comprising: a first stage including first logic gates, each of which performs a first logic operation on a corresponding signal among first to 4 th signals and a first bit of a binary code; a second stage including second logic gates, each of which performs a second logic operation on corresponding output signals of the first logic gates and is reset based on a second bit of the binary code; and a third stage including a third logic gate suitable for performing a third logic operation on output signals of the second logic gates, wherein the number of the first logic gates is 4, the number of the second logic gates is 2,and the number of bits of the binary code is 2.
2. The integrated circuit of claim 1 , wherein the first logic gates are 2-input NAND gates, and the second logic gates are 2-input NAND gates.
3. The integrated circuit of claim 1 , wherein the second logic gates output the output signals fixed to a predetermined logic level when the second logic gates are reset.
4. An integrated circuit, comprising: a first stage including first logic gates, each of which performs a first logic operation on a corresponding signal among first to 8 th signals and a first bit of a binary code; a second stage including second logic gates, each of which performs a second logic operation on corresponding output signals of the first logic gates and is reset based on a second bit of the binary code; a third stage including two third logic gates, each of which performs a third logic operation on corresponding output signals of the second logic gates and is reset based on a third bit of the binary code; and a fourth stage including a fourth logic gate suitable for performing a fourth logic operation on output signals of the two third logic gates, wherein the number of the first logic gates is 8, the number of the second logic gates is 4,and the number of bits of the binary code is 3.
5. An integrated circuit, comprising: a first stage including first logic gates, each of which performs a first logic operation on a corresponding signal among first to N th signals and a first bit of a binary code; a second stage including second logic gates, each of which performs a second logic operation on corresponding output signals of the first logic gates and is reset based on a second bit of the binary code; a third to a log 2 Nth stages each including logic gates suitable for performing a logic operation on output signals of logic gates of a previous stage and being reset based on a particular bit of the binary code; and a (log 2 N)+1th stage including a logic gate suitable for performing a logic operation on output signals of the logic gates of the log 2 Nth stage, wherein N is equal to 2 z , wherein Z is a positive integer and N is greater than or equal to 16.
6. An integrated circuit, comprising: a first logic gate receiving an inverted signal of a first bit of a binary code and a first signal; a second logic gate receiving the first bit of the binary code and a second signal; a third logic gate receiving the inverted signal of the first bit of the binary code and a third signal; a fourth logic gate receiving the first bit of the binary code and a fourth signal; a fifth logic gate receiving output signals of the first logic gate and the second logic gate, and suitable for being reset based on a second bit of the binary code; and a sixth logic gate receiving output signals of the third logic gate and the fourth logic gate, and suitable for being reset based on an inverted signal of the second bit of the binary code.
7. The integrated circuit of claim 6 , wherein the fifth logic gate and the sixth logic gate output signals fixed to a predetermined logic level when the fifth logic gate and the sixth logic gate are reset.
8. The integrated circuit of claim 6 , wherein the first to fourth logic gates are2-input NAND gates.
9. The integrated circuit of claim 8 , wherein the fifth logic gate and the sixth logic gate are 2-input resettable NAND gates.
10. A precharge/active flag generation circuit, comprising: a first stage including first logic gates each of which performs a first logic operation on a corresponding signal among first to 8 th active signals and a first bit of a bank address, wherein the first to 8 th active signals represent whether first to 8 th memory banks are active, respectively; and a second stage including second logic gates each of which performs a second logic operation on output signals of the first logic gates and is reset based on a second bit of the bank address; a third stage including two third logic gates each of which performs a third logic operation on output signals of the second logic gates and is reset based on a third bit of the bank address; and a fourth stage including a fourth logic gate suitable for performing a fourth logic operation on output signals of the two third logic gates to generate a precharge/active flag signal, wherein the number of the first logic gates is 8, the number of the second logic gates is 4,and the number of bits of the bank address is 3.
11. The precharge/active flag generation circuit of claim 10 , wherein the first logic gates are 2-input NAND gates; the second logic gates are 2-input resettable NAND gates; the third logic gates are 2-input resettable NOR gates; and the fourth logic gate is a 2-input NAND gate.
12. The precharge/active flag generation circuit of claim 10 , wherein the second logic gates output signals fixed to a predetermined logic level when the second logic gates are reset.
13. A precharge/active flag generation circuit, comprising: a first stage including first logic gates each of which performs a first logic operation on a corresponding signal among first to 16 th active signals and a first bit of a bank address, wherein the first to 16 th active signals represent whether first to 16 th memory banks are active, respectively; and a second stage including second logic gates each of which performs a second logic operation on output signals of the first logic gates and is reset based on a second bit of the bank address; a third stage including four third logic gates each of which performs a third logic operation on corresponding output signals of the second logic gates and is reset based on a third bit of the bank address; a fourth stage including two fourth logic gates each of which performs a fourth logic operation on corresponding output signals of the third logic gates and is reset based on a fourth bit of the bank address; and a fifth stage including a fifth logic gate suitable for performing a fifth logic operation on output signals of the two fourth logic gates to generate a precharge/active flag signal, wherein the number of the first logic gates is 16, the number of the second logic gates is 8,and the number of bits of the bank address is 4.
14. The precharge/active flag generation circuit of claim 13 , wherein the first logic gates are 2-input NAND gates; the second logic gates are 2-input resettable NAND gates; the third logic gates are 2-input resettable NOR gates; the fourth logic gates are 2-input resettable NAND gates; and the fifth logic gate is an OR gate.
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November 26, 2014
July 26, 2016
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