In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: a first wiring substrate having a first surface; a second wiring substrate arranged as an interposer having a first main surface, a second main surface opposite the first main surface, and first wiring layers arranged closer to the first main surface than the second main surface, the second wiring substrate disposed on the first surface of the first wiring substrate; a first semiconductor chip having a first obverse surface and first electrodes formed on the first obverse surface, the first semiconductor chip being mounted on the first main surface of the second wiring substrate such that the first obverse surface faces the first main surface of the second wiring substrate; and a second semiconductor chip having a second obverse surface and second electrodes formed on the second obverse surface, the second semiconductor chip mounted side by side with the first semiconductor chip on the first main surface of the second wiring substrate such that the second obverse surface faces the first main surface of the second wiring substrate, wherein the first wiring layer of the second wiring substrate includes a first wiring, and wherein the first electrode of the first semiconductor chip is electrically connected with the second electrode of the second semiconductor chip via the first wiring of the second wiring substrate.
2. The semiconductor device according to claim 1 , wherein the first semiconductor chip has a first side, wherein the second semiconductor chip has a second side, wherein the first side of the first semiconductor chip faces the second side of the second semiconductor chip, and wherein the first wiring of the second wiring substrate extends from the first semiconductor chip to the second semiconductor chip and crosses the first side of the first semiconductor chip and the second side of the second semiconductor chip.
3. The semiconductor device according to claim 1 , wherein an overall area of first wiring substrate is greater than an overall area of the second wiring substrate in a plan view.
4. The semiconductor device according to claim 1 , wherein the first semiconductor chip overlaps with the second wiring substrate in a plan view, and wherein the second semiconductor chip overlaps with the second wiring substrate in the plan view.
5. The semiconductor device according to claim 1 , wherein, the first surface of the first wiring substrate has a first area and a second area outside of the first area, and the second wiring substrate is disposed on the first area and a passive component is mounted on the second area.
6. The semiconductor device according to claim 1 , wherein, the first surface of the first wiring substrate has a first area and a second area outside of the first area, and the second wiring substrate is disposed on the first area and a third semiconductor chip mounted on the second area.
7. The semiconductor device according to claim 2 , wherein, the first semiconductor chip has a third side opposite the first side, the second semiconductor chip has a fourth side opposite the second side, the first electrode is disposed closer to the first side than the third side on first obverse surface of the first semiconductor chip, and the second electrode is disposed closer to the second side than the fourth side on the second obverse surface of the second semiconductor chip.
8. The semiconductor device according to claim 7 , wherein, a third electrode is formed on the first obverse surface of the first semiconductor chip and is disposed closer to the third side than the first side on first obverse surface of the first semiconductor chip, a fourth electrode is formed on the second obverse surface of the second semiconductor chip and is disposed closer to the fourth side than the second side on second obverse surface of the second semiconductor chip, the first wiring substrate has a second surface opposite the first surface and includes a second wiring, a third wiring, a first external electrode formed on the second surface, and a second external electrode formed on the second surface, the third electrode is electrically connected with the first external electrode of the first wiring substrate via the second wiring of the first wiring substrate, and the fourth electrode is electrically connected with the second external electrode of the first wiring substrate via the third wiring of the first wiring substrate.
9. The semiconductor device according to claim 1 , wherein, the first semiconductor chip includes a plurality of memory chips which are laminated with each other, and the first semiconductor chip is electrically connected between the memory chips via a through electrode.
10. The semiconductor device according to claim 9 , wherein the second semiconductor chip includes a Central Processing Unit.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 27, 2015
August 2, 2016
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