Charge pump circuit and PLL circuit

1. A charge pump circuit, comprising: a constant current circuit configured to have one terminal connected with a power source node; a first node configured to input or output a current; a second node configured to be set to have a potential difference with the first node being less than or equal to a predetermined value; a first transistor configured to have one terminal connected with the first node; a second transistor configured to have one terminal connected with the second node, and to operate inverse to an operation of the first transistor; and a third transistor configured to be connected between a connection node, to which another terminal of the first transistor and another terminal of the second transistor are connected, and another terminal of the constant current circuit, wherein the third transistor has a gate connected with a constant voltage source, and functions as a constant current source, and the constant current circuit is a transistor configured to have a gate connected with a constant voltage source different from the constant voltage source connected with the gate of the third transistor.

2. The charge pump circuit, as claimed in claim 1 , further comprising: a diode configured to be connected with the second node; and a current generation circuit configured to generate a greater constant current than that of the constant current circuit, and to have the constant current flow in the diode.

3. The charge pump circuit, as claimed in claim 2 , wherein the current generation circuit includes a transistor configured to have a gate connected with the constant voltage source connected with the gate of the third transistor.

4. The charge pump circuit, as claimed in claim 2 , wherein the diode includes a diode-connected transistor.

5. A charge pump circuit, comprising: a first constant current circuit configured to have one terminal connected with a first power source node; a second constant current circuit configured to have one terminal connected with a second power source node having a lower potential than that of the first power source node; a first node configured to input or output a current; a second node configured to be set to have a potential difference with the first node being less than or equal to a predetermined value; a first high-side transistor configured to have one terminal connected with the first node; a first low-side transistor configured to have one terminal connected with the first node; a second high-side transistor configured to have one terminal connected with the second node, and to operate inverse to an operation of the first high-side transistor; a second low-side transistor configured to have one terminal connected with the second node, and to operate inverse to an operation of the first low-side transistor; a third high-side transistor configured to be connected between a first connection node, to which another terminal of the first high-side transistor and another terminal of the second high-side transistor are connected, and another terminal of the first constant current circuit; and a third low-side transistor configured to be connected between a second connection node, to which another terminal of the first low-side transistor and another terminal of the second low-side transistor are connected, and another terminal of the second constant current circuit, wherein the third high-side transistor has a gate connected with a first constant voltage source, and functions as a constant current source, wherein the third low-side transistor has a gate connected with a second constant voltage source having a lower voltage than that of the first constant voltage source, and functions as a constant current source, the first constant current circuit is a transistor configured to have a gate connected with a third constant voltage source having a higher voltage than that of the first constant voltage source, and the second constant current circuit is a transistor configured to have a gate connected with a fourth constant voltage source having a lower voltage than that of the second constant voltage source.

6. The charge pump circuit, as claimed in claim 5 , further comprising: a diode configured to be connected with the second node; and a current generation circuit configured to generate a greater constant current than that of the second constant current circuit, and to have the constant current flow in the diode.

7. The charge pump circuit, as claimed in claim 6 , wherein the current generation circuit includes a transistor configured to have a gate connected with the first constant voltage source.

8. A PLL circuit, comprising: a phase frequency comparator configured to output a phase difference signal corresponding to a phase difference between a reference frequency signal and a predetermined frequency signal received as inputs; the charge pump circuit, as claimed in claim 5 , configured to have the first high-side transistor, the first low-side transistor, the second high-side transistor and the second low-side transistor operate, and to have an electric charge output from the first node, depending on the phase difference signal output from the phase frequency comparator; a loop filter configured to accumulate the electric charge output from the charge pump circuit; a voltage-controlled oscillator configured to oscillate at a frequency corresponding to a voltage generated by the electric charge stored in the loop filter, to output an output frequency signal obtained by multiplying the reference frequency signal by a predetermined ratio; and a frequency divider configured to divide the output frequency signal output from the voltage-controlled oscillator, by the predetermined ratio, and to output the predetermined frequency signal.