A method is provided for fabricating a junction-less transistor. The method includes providing a semiconductor substrate having a dielectric layer; and forming a semiconductor layer including a first heavily doped layer formed on the dielectric layer, a lightly doped layer formed on the first heavily doped layer and a second heavily doped layer formed on the lightly doped layer. The method also includes etching the semiconductor layer and the dielectric layer to form trenches to expose side surfaces of a portion of the semiconductor layer and a portion of the dielectric layer; and removing the portion of the dielectric layer between the adjacent trenches to form a chamber. Further, the method includes forming a gate structure around the portion of the semiconductor layer between the adjacent trenches; and forming a source region and a drain region in the semiconductor layer at both sides of the gate structure.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A junction-less transistor, comprising: a substrate; a dielectric layer on the substrate, wherein the dielectric layer includes an opening exposing a surface portion of the substrate; a semiconductor layer having a first heavily doped layer formed on the dielectric layer, a lightly doped layer formed on the first heavily doped layer and a second heavily doped layer formed on the lightly doped layer, wherein the semiconductor layer includes an overhung portion on the opening of the dielectric layer; a plurality of gate structures with each gate structure covering side surfaces, a top surface and a bottom surface of the overhung portion of the semiconductor layer; and a source region and a drain region formed in the semiconductor layer at both sides of the gate structure, wherein: the first heavily doped layer, the lightly doped layer, and the second heavily doped layer of the overhung portion of the semiconductor layer provide a sandwich doping profile as a channel region of the junction-less transistor, and the lightly doped layer has a doping concentration in a range of 1E18 atom/cm 3 to 1E20 atom/cm 3 , and each of the first and second heavily doped layers has a doping concentration greater than the lightly doped layer.
2. The junction-less transistor according to claim 1 , wherein: a doping type of the first heavily doped layer, the lightly doped layer and the second heavily doped layer is same as a doping type of the source region and the drain region.
3. The junction-less transistor according to claim 1 , wherein: a doping concentration of the first heavily doped layer is in a range of 1E10 atom/cm 3 to 1E21 atom/cm 3 .
4. The junction-less transistor according to claim 1 , wherein: a doping concentration of the second heavily doped layer is in a range of 1E10 atom/cm 3 to 1E21 atom/cm 3 .
5. The junction-less transistor according to claim 1 , wherein: a width of the overhung portion of the semiconductor layer is in a range of approximately 10 nm-200 nm.
6. The junction-less transistor according to claim 1 , wherein: a thickness of the lightly doped layer is twice of a thickness of the first heavily doped layer.
7. The junction-less transistor according to claim 1 , wherein: the gate structure is a dual gate structure having a top gate on the top surface of the first heavily doped and a bottom gate on the bottom surface of the first heavily doped layer.
8. The junction-less transistor according to claim 1 , wherein: the first heavily doped layer is made of Si, Ge, or SiGe; the second heavily doped layer is made of Si, Ge, or SiGe; and the lightly doped layer is made of Si, Ge, or SiGe.
9. The junction-less transistor according to claim 1 , wherein: a thickness of the first heavily doped layer is in a range of approximately 2 nm to 200 nm; and a thickness of the second heavily doped layer is in a range of approximately 2 nm to 200 nm.
10. The junction-less transistor according to claim 1 , wherein: the semiconductor substrate and the dielectric layer are made of materials having an etching selectivity.
11. The junction-less transistor according to claim 1 , wherein: each of the source region and the drain region has a doping concentration in a range of approximately 1E18 atom/cm 3 to 1E20 atom/cm 3 .
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 18, 2015
August 9, 2016
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.