A design structure for a semiconductor structure is disclosed. The semiconductor structure can include a substrate, a set of semiconductor fins positioned on the substrate and positioned approximately parallel lengthwise to one another, a first gate layer and a second gate layer deposited on the substrate and on the set of semiconductor fins approximately perpendicular lengthwise to the set of semiconductor fins. The semiconductor structure can include an interconnect layer deposited on the substrate and on the set of semiconductor fins approximately perpendicular lengthwise to the set of semiconductor fins. The interconnect layer can be positioned between the first gate layer and the second gate layer at a first interconnect distance from the first gate layer and a second interconnect distance from the second gate layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming a semiconductor structure comprising: forming a set of semiconductor fins on a substrate, the set of semiconductor fins positioned approximately parallel lengthwise to one another, each of the set of semiconductor fins separated from one another by a fin distance; forming a first gate layer having a first gate width, the first gate layer deposited on the substrate and on the set of semiconductor fins approximately perpendicular lengthwise to the set of semiconductor fins, the first gate layer directly contacting sidewalls of each of the set of semiconductor fins; forming a second gate layer having a second gate width, the second gate layer deposited on the substrate and on the set of semiconductor fins approximately perpendicular lengthwise to the set of semiconductor fins, the second gate layer directly contacting sidewalls of each of the set of semiconductor fins, the first gate layer and the second gate layer positioned approximately parallel with one another and separated by a gate distance; and forming an interconnect layer deposited on the substrate and on the set of semiconductor fins approximately perpendicular lengthwise to the set of semiconductor fins, the interconnect layer directly contacting sidewalls of each of the set of semiconductor fins, the interconnect layer positioned between the first gate layer and the second gate layer at a first interconnect distance from the first gate layer and a second interconnect distance from the second gate layer.
2. The method of claim 1 , further comprising: forming, prior to forming the interconnect layer, an insulator layer directly on the substrate, on the set of semiconductor fins, and on the first and second gate layers; planarizing, prior to forming the interconnect layer, the insulator layer down to the first and second gates to reveal a portion of the first and second gates.
3. The method of claim 2 , wherein: forming the interconnect layer includes: masking the first and second gate layers, masking a portion of the insulator layer, and leaving unmasked a channel, the channel positioned between the first and second gates and having a width approximately equal to an interconnect width of the interconnect layer; etching the insulator layer in the channel to reveal a portion of the set of semiconductor fins and the substrate; and forming the interconnect layer on the substrate and the set of semiconductor fins in the channel.
4. The method of claim 1 , wherein: the first interconnect distance and the second interconnect distance are approximately equal.
5. The method of claim 1 , wherein: the interconnect layer is constructed from conductive material, the conductive material electrically connecting each of the set of semiconductor fins.
6. The method of claim 1 , wherein: the first gate layer includes a first dielectric layer directly on the substrate and on the set of semiconductor fins and a first poly-silicon layer directly on the first dielectric layer.
7. The method of claim 1 , wherein: the semiconductor structure is constructed according to a technology node approximately in a range of 5 nanometers to 45 nanometers.
8. The method of claim 1 , wherein: The set of semiconductor fins each have dimensions including a fin width and a fin height, wherein fin height is approximately twice as large as the fin width and the fin distance is approximately one and a half times the fin width.
9. The method of claim 1 , wherein: the first gate width and the second gate width are approximately equal, and the gate distance is a value approximately three times the first gate width.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 16, 2014
September 13, 2016
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