Semiconductor package including multiple chips and separate groups of leads

1. A semiconductor package comprising: a packaging substrate including a plurality of terminals on the packaging substrate, the plurality of terminals including, a first group of terminals configured to receive respective channel lines of a first channel from a controller, wherein the first group of terminals includes a chip enable terminal configured to receive a chip enable channel line of the first channel from the controller, and a second group of terminals configured to receive respective channel lines of a second channel from the controller; a first semiconductor chip group on the packaging substrate, wherein the first semiconductor chip group includes a first plurality of semiconductor chips electrically connected to terminals of the first group of terminals; a second semiconductor chip group on the packaging substrate, wherein the second semiconductor chip group includes a second plurality of semiconductor chips electrically connected to terminals of the second group of terminals; and a chip enable signal line providing electrical connection between the chip enable terminal and first and second semiconductor chips of the first plurality of semiconductor chips, wherein upon the chip enable signal line receiving an active chip enable signal, one of the first and second semiconductor chips is activated by a logic signal at an address line.

2. The semiconductor package of claim 1 , wherein in response to the logic signal at the address line, a first circuitry of the first semiconductor chip is activated and a second circuitry of the second semiconductor chip is not activated, wherein the first and second circuitries are substantially the same.

3. The semiconductor package of claim 1 , wherein the second group of terminals includes a second chip enable terminal configured to receive a chip enable channel line of the second channel from the controller, the semiconductor package further comprising: a second chip enable signal line providing electrical connection between the chip enable terminal and first and second semiconductor chips of the second semiconductor chip group.

4. The semiconductor package of claim 1 , wherein the first group of terminals includes a second chip enable terminal configured to receive a second chip enable channel line of the first channel from the controller, the semiconductor package further comprising: a second chip enable signal line providing electrical connection between the second chip enable terminal and third and fourth semiconductor chips of the first semiconductor chip group.

5. The semiconductor package of claim 4 , wherein the first group of terminals includes an input/output terminal configured to receive an input/output channel line of the first channel from the controller, the semiconductor package further comprising: an input/output signal line providing electrical connection between the input/output terminal and the first, second, third, and fourth semiconductor chips of the first semiconductor chip group.

6. The semiconductor package of claim 1 , wherein the controller comprises a memory controller, wherein the first plurality of semiconductor chips of the first semiconductor chip group comprise a first plurality of semiconductor memory chips, and wherein the second plurality of semiconductor chips of the second semiconductor chip group comprise a second plurality of semiconductor memory chips.

7. The semiconductor package of claim 6 , wherein the first group of terminals includes a plurality of input/output terminals configured to receive respective input/output channel lines of the first channel, a read/busy terminal configured to receive a read/busy channel line of the first channel, and a write protect terminal configured to receive a write protect channel line of the first channel, and wherein the second group of terminals includes a chip enable terminal configured to receive a chip enable channel line of the second channel, a plurality of input/output terminals configured to receive respective input/output channel lines of the second channel, a read/busy terminal configured to receive a read/busy channel line of the second channel, and a write protect terminal configured to receive a write protect channel line of the second channel.

8. The semiconductor package of claim 1 , wherein the chip enable signal line comprises a wire bond.

9. The semiconductor package of claim 1 , wherein the controller comprises a memory controller, wherein the first semiconductor chip group includes four semiconductor memory chips, wherein the second semiconductor chip group includes four semiconductor memory chips, wherein the first group of terminals includes a second chip enable terminal configured to receive a second chip enable channel line of the first channel from the memory controller, wherein the second group of terminals includes first and second chip enable terminals configured to receive respective first and second chip enable channel lines of the second channel from the memory controller, the semiconductor package further comprising: a second chip enable signal line providing electrical connection between the second chip enable terminal of the first group of terminals and third and fourth semiconductor memory chips of the first semiconductor chip group; a third chip enable signal line providing electrical connection between the first chip enable terminal of the second group of terminals and first and second semiconductor memory chips of the second semiconductor chip group; and a fourth chip enable signal line providing electrical connection between the second chip enable terminal of the second group of terminals and third and fourth semiconductor memory chips of the second semiconductor chip group.

10. The semiconductor package of claim 9 , wherein the first group of terminals includes an input/output terminal configured to receive an input/output channel line of the first channel from the memory controller, and wherein the second group of terminals includes an input/output terminal configured to receive an input/output channel line of the second channel from the memory controller, the semiconductor package further comprising: first input/output signal line providing electrical connection between the input/output terminal of the first group of terminals and each of the first, second, third, and fourth semiconductor memory chips of the first plurality of semiconductor memory chips; and a second input/output signal line providing electrical connection between the input/output terminal of the second group of terminals and each of the first, second, third, and fourth semiconductor memory chips of the first plurality of semiconductor memory chips.

11. A semiconductor memory comprising: a packaging substrate including a chip enable terminal configured to receive a first chip enable channel line from a memory controller; and first and second semiconductor memory chips on the packaging substrate, wherein an electrical connection is provided between the chip enable terminal and each of the first and second semiconductor memory chips, wherein upon the chip enable signal line receiving an active chip enable signal, one of the first and second semiconductor chips is activated by a logic signal at an address line.

12. The semiconductor of claim 11 , wherein in response to the logic signal, a first circuitry of the first semiconductor chip is activated and a second circuitry of the second semiconductor chip is not activated, wherein the first and second circuitries are substantially the same.

13. The semiconductor memory of claim 11 , wherein the chip enable terminal is a first chip enable terminal, wherein the electrical connection is a first electrical connection, wherein the packaging substrate further includes a second chip enable terminal configured to receive a second chip enable channel line from the memory controller, the semiconductor memory further comprising: a third semiconductor memory chip on the packaging substrate, wherein a second electrical connection is provided between the second chip enable terminal and the third semiconductor memory chip.

14. The semiconductor memory of claim 13 , wherein the packaging substrate further includes a first input/output terminal configured to receive a first input/output channel line from the memory controller and a second input/output terminal configured to receive a second input/output channel line from the memory controller, wherein a third electrical connection is provided between the first input/output terminal and each of the first and second semiconductor memory chips, wherein the first and second semiconductor memory chips are free of electrical coupling with the second input/output terminal, wherein a fourth electrical connection is provided between the second input/output terminal and the third semiconductor memory chip, and wherein the third semiconductor memory chip is free of electrical coupling with the first input/output terminal.

15. The semiconductor memory of claim 14 , further comprising: a fourth semiconductor memory chip on the packaging substrate, wherein the second electrical connection is provided between the second chip enable terminal and the third and fourth semiconductor memory chips, and wherein the fourth electrical connection is provided between the second input/output terminal and the third and fourth semiconductor memory chips.

16. The semiconductor memory of claim 15 , wherein the packaging substrate further includes a third chip enable terminal configured to receive a third chip enable channel line from the memory controller, the semiconductor memory further comprising: fifth and sixth semiconductor memory chips on the packaging substrate, wherein a fifth electrical connection is provided between the third chip enable terminal and each of the fifth and sixth semiconductor memory chips, and wherein the third electrical connection is provided between the first input/output terminal and each of the first, second, fifth, and sixth semiconductor memory chips.

17. The semiconductor memory of claim 13 , wherein the first chip enable channel line comprises a channel line of a first channel from the memory controller, and wherein the second chip enable channel line comprises a channel line of a second channel from the memory controller.

18. The semiconductor memory of claim 17 , wherein the packaging substrate further comprises a first plurality of input/output terminals configured to receive respective input/output channel lines of the first channel and electrically connected to the first and second semiconductor memory chips, and a second plurality of input/output terminals configured to receive respective input/output channel lines of the second channel and electrically connected to the third semiconductor memory chip.

19. A semiconductor memory system comprising: a memory controller; and a semiconductor memory coupled with the memory controller, the semiconductor memory comprising a packaging substrate including a first chip enable terminal configured to receive a first chip enable channel line from the memory controller, and a second chip enable terminal configured to receive a second chip enable channel line from the memory controller, first and second semiconductor memory chips on the packaging substrate, wherein a first electrical connection is provided between the first chip enable terminal and each of the first and second semiconductor memory chips and wherein, and a third semiconductor memory chip on the packaging substrate, wherein a second electrical connection is provided between the second chip enable terminal and the third semiconductor memory chip, wherein upon the chip enable signal line receiving an active chip enable signal, one of the first and second semiconductor chips is activated by a logic signal at an address line.

20. The semiconductor of claim 19 , wherein in response to the logic signal, a first circuitry of the first semiconductor chip is activated and a second circuitry of the second semiconductor chip is not activated, wherein the first and second circuitries are substantially the same.