Provided is a semiconductor device having improved performance. Over a semiconductor substrate, a dummy control gate electrode is formed via a first insulating film. Over the semiconductor substrate, a memory gate electrode for a memory cell is formed via a second insulating film having an internal charge storage portion so as to be adjacent to the dummy control gate electrode. At this time, the height of the memory gate electrode is adjusted to be lower than the height of the dummy control gate electrode. Then, a third insulating film is formed so as to cover the dummy control gate electrode and the memory gate electrode. Then, the third insulating film is polished to expose the dummy control gate electrode. At this time, the memory gate electrode is not exposed. Then, the dummy control gate electrode is removed and replaced with a metal gate electrode.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of manufacturing a semiconductor device including a memory cell of a nonvolatile memory, comprising the steps of: (a) providing a semiconductor substrate; (b) forming a first dummy gate electrode over the semiconductor substrate via a first insulating film; (c) forming a first gate electrode for the memory cell over the semiconductor substrate via a second insulating film having an internal charge storage portion such that the first gate electrode for the memory cell is adjacent to the first dummy gate electrode; (d) forming a first interlayer insulating film so as to cover the first dummy gate electrode and the first gate electrode therewith; (e) polishing the first interlayer insulating film to expose the first dummy gate electrode; (f) after the step (e), removing the first dummy gate electrode; and (g) forming a second gate electrode for the memory cell in a first trench as a region resulting from the removal of the first dummy gate electrode in the step (f), wherein the second gate electrode is a metal gate electrode, wherein a height of the first gate electrode formed in the step (c) is lower than a height of the first dummy gate electrode, and wherein, in the step (e), the first gate electrode is not exposed.
2. The method of manufacturing a semiconductor device according to claim 1 , wherein the first gate electrode is made of silicon.
3. The method of manufacturing a semiconductor device according to claim 2 , wherein the first dummy gate electrode is made of silicon.
4. The method of manufacturing a semiconductor device according to claim 3 , wherein the first gate electrode formed in the step (c) is adjacent to the first dummy gate electrode via the second insulating film.
5. The method of manufacturing a semiconductor device according to claim 1 , wherein, in the step (g), a first conductive film is embedded in the first trench via a high-dielectric-constant insulating film to form the second gate electrode.
6. The method of manufacturing a semiconductor device according to claim 1 , wherein, in the step (b), a first multi-layer body including the first dummy gate electrode, and a first cap insulating film over the first dummy gate electrode is formed over the semiconductor substrate via the first insulating film, wherein, in the step (d), the first interlayer insulating film is formed so as to cover the first multi-layer body and the first gate electrode, and wherein, in the step (e), the first interlayer insulating film and the first cap insulating film are polished to expose the first dummy gate electrode.
7. The method of manufacturing a semiconductor device according to claim 1 , wherein the step (c) includes the steps of: (c1) forming the second insulating film over the semiconductor substrate so as to cover the first dummy gate electrode therewith; (c2) forming a first silicon film for the first gate electrode over the second insulating film; and (c3) etching back the first silicon film to form the first gate electrode.
8. The method of manufacturing a semiconductor device according to claim 1 , further comprising, after the step (c) and before the step (d), the step of: (c4) forming a first side-wall insulating film over each of respective side walls of the first dummy gate electrode and the first gate electrode.
9. The method of manufacturing a semiconductor device according to claim 8 , further comprising, after the step (c4) and before the step (d), the step of: (c5) forming a first semiconductor region for a source or drain of the memory cell in the semiconductor substrate by an ion implantation method.
10. The method of manufacturing a semiconductor device according to claim 9 , further comprising, after the step (c) and before the step (c4), the step of: (c6) forming a second semiconductor region for the source or drain of the memory cell in the semiconductor substrate by an ion implantation method, wherein the first semiconductor region has an impurity concentration higher than that of the second semiconductor region.
11. The method of manufacturing a semiconductor device according to claim 1 , further comprising, after the step (b) and before the step (c), the steps of: (b1) forming a second side-wall insulating film over a side wall of the first dummy gate electrode over which the first gate electrode is to be formed later; (b2) after the step (b1), forming a third semiconductor region for a source or drain of the memory cell in the semiconductor substrate by an ion implantation using the second side-wall insulating film as an ion implantation inhibiting mask; and (b3) after the step (b2), removing the second side-wall insulating film.
12. The method of manufacturing a semiconductor device according to claim 11 , wherein a height of the second side-wall insulating film formed in the step (b1) is larger than a height of the first gate electrode formed in the step (c).
13. The method of manufacturing a semiconductor device according to claim 1 , further comprising, after the step (c) and before the step (d), the step of: (c7) forming a second dummy gate electrode over the semiconductor substrate via a third insulating film, wherein, in the step (d), the first interlayer insulating film is formed so as to cover the first dummy gate electrode, the second dummy gate electrode, and the first gate electrode, wherein, in the step (e), the first interlayer insulating film is polished to expose the first and second dummy gate electrodes, wherein, in the step (f), the first and second dummy gate electrodes are removed, and wherein, in the step (g), the second gate electrode is formed in the first trench and a third gate electrode for a MISFET other than that of the memory cell is formed in a second trench as a region resulting from the removal of the second dummy gate electrode in the step (f).
14. The method of manufacturing a semiconductor device according to claim 13 , wherein each of the second and third gate electrodes is a metal gate electrode.
15. The method of manufacturing a semiconductor device according to claim 14 , wherein the first and second dummy gate electrodes are formed of the same silicon film.
16. The method of manufacturing a semiconductor device according to claim 15 , wherein, in the step (c7), over the semiconductor substrate, the second dummy gate electrode is formed via the third insulating film and a fourth gate electrode for the MISFET other than that of the memory cell is formed via a fourth insulating film, wherein the first dummy gate electrode, the second dummy gate electrode, and the fourth gate electrode are formed of the same silicon film, wherein, in the step (d), the first interlayer insulating film is formed so as to cover the first dummy gate electrode, the first gate electrode, the second dummy gate electrode, and the fourth gate electrode, wherein, in the step (e), the first interlayer insulating film is polished to expose the first dummy gate electrode, the second dummy gate electrode, and the fourth gate electrode, and wherein, in the step (f), the fourth gate electrode is not removed.
17. The method of manufacturing a semiconductor device according to claim 16 , further comprising, after the step (c) and before the step (d), the step of: (c8) forming a first side-wall insulating film over each of respective side walls of the first dummy gate electrode, the first gate electrode, the second dummy gate electrode, and the fourth gate electrode, wherein a thickness of the first side-wall insulating film formed over the side wall of the fourth gate electrode is larger than a thickness of the first side-wall insulating film formed over each of the respective side walls of the first dummy gate electrode, the first gate electrode, and the second dummy gate electrode.
18. The method of manufacturing a semiconductor device according to claim 17 , wherein, in the step (b), over the semiconductor substrate, a first multi-layer body including the first dummy gate electrode, and a first cap insulating film over the first dummy gate electrode is formed via the first insulating film, wherein, in the step (c7), over the semiconductor substrate, a second multi-layer body including the second dummy gate electrode, and a second cap insulating film over the second dummy gate electrode is formed via the third insulating film and a third multi-layer body including the fourth gate electrode, and a third cap insulating film over the fourth gate electrode is formed via the fourth insulating film, wherein, in the step (d), the first interlayer insulating film is formed so as to cover the first gate electrode, the first multi-layer body, the second multi-layer body, and the third multi-layer body, wherein, in the step (e), the first interlayer insulating film, the first cap insulating film, the second cap insulating film, and the third cap insulating film are polished to expose the first dummy gate electrode, the second dummy gate electrode, and the fourth gate electrode, and wherein a height of the first multi-layer body formed in the step (b) is larger than a thickness of the first side-wall insulating film formed over the side wall of the fourth gate electrode in the step (c8).
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 28, 2015
October 4, 2016
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