A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus, comprising: a latch configured to receive and latch a command; and a command decoder coupled to the latch and configured to receive the command and receive a bank signal indicative of a state of a bank, the command decoder configured to perform a first operation responsive, at least in part, to a first command and the bank signal indicating the bank is in a first state and further configured to perform a second operation responsive, at least in part, to the first command and the bank signal indicating the bank is in a second state, the command decoder further configured to perform a third operation responsive, at least in part, to a second command and the bank signal indicating the bank is in the first state.
2. The apparatus of claim 1 , further comprising: bank control logic configured to provide the bank signal to the command decoder; and wherein the first state corresponds to a first operating state of the bank and the second state corresponds to a second operating state of the bank.
3. The apparatus of claim 1 , wherein the first operation is one of plurality of bank active operations and the second operation is one of plurality of bank inactive operations.
4. The apparatus of claim 3 , wherein at least one of the plurality of bank active operations is configured to switch the bank to switch to a third state.
5. The apparatus of claim 1 , wherein the command comprises at least one of a row address select signal, a write enable signal, or an A10 signal.
6. The apparatus of claim 1 , wherein the apparatus is included in a memory.
7. A method of decoding command signals applied to a memory bank, comprising: monitoring an operating state of the memory bank, the memory bank having a precharged operating state and an active operating state; performing an operation from a first set of operations in accordance with a first combination of the command signals responsive, at least in part, to the memory bank is operating in the precharged operating state; and performing an operation from a second set of operations in accordance with second combination of the command signals responsive, at least in part, to the memory bank is operating in the active second operating state.
8. The method of claim 7 , further comprising: performing an operation from a third set of operations in accordance with the command signals while the memory bank is in a third operating state.
9. The method of claim 8 , further comprising: monitoring a logic level of a signal applied to the memory bank.
10. The method of claim 9 , wherein said monitoring a logic level of a signal applied to the memory bank comprises: monitoring the logic state of an address signal.
11. The method of claim 8 , wherein said performing an operation from the first set of operations in accordance with the command signals comprises: performing an operation that results in the memory bank changing from the precharged operating state to the third operating state.
12. The method of claim 11 , wherein the thud operating state comprises a power down state.
13. The method of claim 7 , wherein said performing an operation from a first set of operations in accordance with the command signals while the memory bank is in the precharged operating state comprises: performing a first mode of an operation in response to the signal having a first logic level and performing a second mode of the operation in response to the signal having the second logic level.
14. The method of claim 7 , wherein said monitoring an operating state of the memory bank comprises: receiving a bank state signal; and determining the operating state of the memory bank based, at least in part, on the bank state signal.
15. A method, comprising: receiving a command; receiving a bank state signal indicative of a state of a memory bank; performing a first operation based, at least in part, on a first command and the bank state signal indicating the bank has a first state; performing as second operation based, at least in part, on the first command and the bank state signal indicating the bank has a second state; and performing a third operation based least in part, on a second command and the bank state signal indicating the bank has the first state.
16. The method of claim 15 , further comprising: performing a third operation based, at least in part, on the bank state signal indicating the memory bank has a third state.
17. The method of claim 14 , wherein said performing the first operation based, at least in part, on the bank state signal indicating the memory bank has a first state comprises: performing an operation that causes the memory bank to change from the first state to a third state.
18. The method of claim 14 , wherein the first state corresponds to an active state and the second state corresponds to an inactive state.
19. The method of claim 14 , wherein said performing the first operation based, at least in part, on the bank state signal indicating the bank has a first state comprises: generating a set of internal signals to perform the first operation.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 5, 2012
October 11, 2016
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