An integrated electronic package includes an integrated circuit (IC) die and conductive discrete components. Electrical interconnects are formed directly between bond pads on an active side of the IC die and contacts on the conductive discrete components without an intervening lead frame. The IC die, conductive discrete components and electrical interconnects are embedded in an encapsulation material. Contact surfaces of at least some of the conductive discrete components are exposed from the encapsulation material and can be attached to a printed circuit board in order to mount the integrated electronic package to the printed circuit board.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated electronic package comprising: an integrated circuit (IC) die having an active side at which bond pads are located, and a back side opposing said active side; a surface mount component having first and second electrically conductive contacts separated from one another by a body portion spanning between said first and second contacts, wherein said surface mount component comprises at least one of a resistor, a capacitor, an inductor, and a diode; a first electrical interconnect formed directly between one of said bond pads and said first contact without an intervening lead frame; a second electrical interconnect formed directly between a second one of said bond pads and said second contact; and encapsulation material formed over said IC die, said surface mount component, and said electrical interconnect, wherein said first contact and said body portion of said surface mount component are embedded within said encapsulation material and a contact surface of said second contact is exposed from said encapsulation material.
2. The integrated electronic package of claim 1 wherein said contact surface of said second contact is a first contact surface, and said first contact has a second contact surface that is exposed from said encapsulation material.
3. The integrated electronic package of claim 1 further comprising a chip-based device, said chip-based device being one of a chip resistor, a chip resistor array, and a chip capacitor, said chip-based device including: a body portion having a third contact located on said body portion; and a metallization layer located on a surface of said body portion, wherein said third contact and said body portion are embedded within said encapsulation material, and said metallization layer is exposed from said encapsulation material.
4. The integrated electronic package of claim 1 wherein said first contact is formed from a material that melts at a first temperature, said first temperature being greater than a second temperature used to perform a reflow soldering process.
5. The integrated electronic package of claim 4 wherein said material used to form said first contact is at least one of a gold, a copper, a nickel, and a solder wettable material.
6. An integrated electronic package comprising: an integrated circuit (IC) die having an active side at which bond pads are located, and a back side opposing said active side; a surface mount component having first and second electrically conductive contacts separated from one another by a body portion spanning between said first and second contacts, wherein said surface mount component comprises at least one of a resistor, a capacitor, an inductor, and a diode, and a material used to form said first and second contacts is at least one of a gold, a copper, a nickel, and a solder wettable material; a first electrical interconnect formed directly between one of said bond pads and said first contact without an intervening lead frame; a second electrical interconnect formed directly between a second one of said bond pads and said second contact; and encapsulation material formed over said IC die, said surface mount component, and said electrical interconnect, wherein said first electrically conductive contact includes a first contact surface that is exposed from said encapsulation material and configured to be attached to a printed circuit board.
7. The integrated electronic package of claim 6 wherein said second electrically conductive contact has a second contact surface that is exposed from said encapsulation material.
8. The integrated electronic package of claim 7 wherein said second contact is formed from said at least one of said gold, said copper, said nickel, and said solder wettable material.
9. The integrated electronic package of claim 6 wherein said second contact is formed from said at least one of said gold, said copper, said nickel, and said solder wettable material.
10. The integrated electronic package of claim 6 further comprising a chip-based device, said chip-based device being one of a chip resistor, a chip resistor array, and a chip capacitor, said chip-based device including; a body portion having a third contact located on said body portion; and a metallization layer located on a surface of said body portion, wherein said third contact and said body portion are embedded within said encapsulation material, and said metallization layer is exposed from said encapsulation material.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 5, 2014
October 18, 2016
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