Patentable/Patents/US-9478571
US-9478571

Buried channel deeply depleted channel transistor

PublishedOctober 25, 2016
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.

Patent Claims
9 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A method of fabricating a semiconductor device, the method comprising: providing a semiconductor substrate having one or more first device regions of a first conductivity type; adding at least one first dopant of the first conductivity type into at least one of the first device regions to define a screening layer of the first conductivity type at the surface of the semiconductor substrate and having an effective doping density that is substantially higher than an effective doping density of the first device regions; forming a substantially undoped layer of semiconducting material at least over the at least one of the first device regions; adding at least one second dopant of a second conductivity type into the substantially undoped layer over the at least one of the first device regions to define a channel layer above the screening layer; and forming gate structures and associated source and drain regions of the second conductivity type separated by a channel length in the first device regions to define MOSFET devices.

2

2. The method of claim 1 , wherein the forming comprises depositing a blanket epitaxial layer of the semiconductor material over the surface of the semiconductor substrate.

3

3. The method of claim 1 , wherein the adding of the at least one first dopant comprises implanting the at least one first dopant using implant conditions that result in an effective doping density of the first conductivity type in the screening region that is between about 10 18 cm −3 to 5×10 20 cm −3 .

4

4. The method of claim 1 , wherein the adding of the at least one second dopant comprises implanting the at least one second dopant using implant conditions that result in an effective doping density of the second conductivity type in the channel layer to be much less than an effective doping density of the source region and the drain region, by up to a few orders of magnitude or more.

5

5. The method of claim 1 , wherein the forming of the source and drain regions comprises implanting one or more dopants of the second conductivity type in the at least one of the first device regions using implant conditions that result in the screening layer being located below and between the source and drain regions.

6

6. A method of fabricating a semiconductor device, the method comprising: providing a semiconductor substrate having one or more first device regions of a first conductivity type; adding at least one first dopant of the first conductivity type into at least one of the first device regions to define a screening layer of the first conductivity type below the surface of the semiconductor substrate and a substantially undoped channel layer above the screening layer, the screening layer having an effective doping density that is substantially higher than an effective doping density of the first device regions; adding at least one second dopant of a second conductivity type into the substantially undoped channel layer; and forming gate structures and associated source and drain regions of the second conductivity type separated by a channel length in the first device regions to define MOSFET devices.

7

7. The method of claim 6 , wherein the adding of the at least one first dopant comprises implanting the at least one first dopant using implant conditions that result in an effective doping density of the first conductivity type in the screening layer that is between about 10 18 cm −3 to 5×10 20 cm −3 .

8

8. The method of claim 6 , wherein the adding of the at least one second dopant comprises implanting the at least one second dopant using implant conditions that result in an effective doping density of the second conductivity type in the channel layer to be much less than an effective doping density of the source region and the drain region, by up to a few orders of magnitude or more.

9

9. The method of claim 6 , wherein the forming of the source and drain regions comprises implanting one or more dopants of the second conductivity type in the at least one of the first device regions using implant conditions that result in the screening layer being located below and between the source and drain regions.

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Patent Metadata

Filing Date

May 23, 2014

Publication Date

October 25, 2016

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