A thin film transistor includes a gate electrode, a gate insulating layer, a channel layer, an etching stop layer, two contact holes, a source, and a drain. The gate insulating layer covers the gate electrode. The channel layer is arranged on the gate insulating layer corresponding to the gate electrode. The etching stop layer covers the channel layer and includes an organic stop layer and a hard mask layer, the hard mask layer is located on a surface of the organic stop layer opposite to the channel layer to enhance a hardness of the organic stop layer. The two contact holes pass through the etching stop layer. The source connects to the channel via one contact hole, and the drain connects to the channel via the other contact hole.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A thin film transistor, comprising: a gate electrode; a gate insulating layer covering the gate electrode; a channel layer arranged on the gate insulating layer corresponding to the gate electrode; an etching stop layer in a double-layer structure covering the channel layer and comprising an organic stop layer and a hard mask layer, the hard mask layer located on a surface of the organic stop layer opposite to the channel layer; a plurality of contact holes passing through the etching stop layer; a source connecting to the channel layer via one of the plurality of contact holes; and a drain connecting to the channel layer via the another of the plurality of contact holes; wherein the hard mask layer enhances a hardness of the organic stop layer.
2. The thin film transistor of claim 1 , wherein a photosensitivity of a photoresistor material is better than a photosensitivity of the etching stop layer.
3. The thin film transistor of claim 1 , wherein a thickness of the hard mask layer is less than a thickness of the organic stop layer.
4. The thin film transistor of claim 1 , wherein the hard mask layer is made of a material selected from a group of silicon nitride (SiNx), Silicon oxide (SiOx), silicon fluorion (SiFx), and silicon nitride oxide (SiNxOy).
5. The thin film transistor of claim 1 , wherein a distance between the two through holes is less than ten micrometers.
6. The thin film transistor of claim 5 , wherein the distance between the two through holes is about 3-5 micrometers.
7. The thin film transistor of claim 1 , wherein the channel layer is made of metal-oxide semiconductor materials.
8. The thin film transistor of claim 7 , wherein the channel layer is made of a material selected from a group of indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (InO), gallium oxide (GaO).
9. A display array substrate, comprising: a plurality of gate lines arranged in parallel; a plurality of data lines arranged in parallel and isolatedly intersect with the gate lines; the data lines and the gate lines defining multiple intersections where the data lines cross the gate lines, and a thin film transistor arranged on each of the multiple intersections; the thin film transistor comprising: a gate electrode; a gate insulating layer covering the gate electrode; a channel layer arranged on the gate insulating layer corresponding to the gate electrode; an etching stop layer in a double-layer structure covering the channel layer and comprising an organic stop layer and a hard mask layer, the hard mask layer located on a surface of the organic stop layer opposite to the channel layer; two contact holes passing through the etching stop layer; and a source connecting to the channel via one of the two contact holes; and a drain connecting to the channel via the other of the two contact holes; wherein the hard mask layer enhances a hardness of the organic stop layer.
10. The display array substrate of claim 9 , wherein a photosensitivity of a photoresistor material is better than a photosensitivity of the etching stop layer.
11. The display array substrate of claim 9 , wherein a thickness of the hard mask layer is less than a thickness of the organic stop layer.
12. The display array substrate of claim 9 , wherein the hard mask layer is made of a material selected from a group of silicon nitride (SiNx), Silicon oxide (SiOx), silicon fluorion (SiFx), and silicon nitride oxide (SiNxOy).
13. The display array substrate of claim 9 , wherein a distance between the two through holes is less than ten micrometers.
14. The display array substrate of claim 13 , wherein the distance between the two through holes is about 3-5 micrometers.
15. The display array substrate of claim 9 , wherein the channel layer is made of metal-oxide semiconductor materials.
16. The display array substrate of claim 15 , wherein the channel layer is made of a material selected from a group of indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (InO), gallium oxide (GaO).
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 25, 2014
October 25, 2016
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