Capacitive trans-impedance amplifier circuit with charge injection compensation

1. A capacitive trans-impedance amplifier circuit with charge injection compensation, comprising: an amplifier having at least an inverting input port and an output port; a feedback capacitor connected between the inverting input port of the amplifier and the output port of the amplifier; a reset switch, implemented as a MOS transistor having a gate terminal, a source terminal and a drain terminal, the source terminal and the drain terminal being connected between the inverting input port and the output port of the amplifier, and the gate terminal being controlled by a reset signal, wherein the reset switch is configured to be in a closed or active state for establishing a conductive path between the inverting input port of the amplifier and the output port of the amplifier during a reset phase, and configured to be in an open or inactive state during an integration phase; a photodiode directly connected to the inverting input port of the amplifier; and one or more compensation capacitors that are configured to provide a total compensation charge that has an opposite polarity of a charge injected by the reset switch at the inverting input port, wherein each compensation capacitor is not implemented as a gate oxide or a MOS capacitor, and each compensation capacitor having: a first port connected to a compensation signal that is a static signal or a toggling compensation signal that toggles between a first compensation voltage value and a second compensation voltage value, and a second port connected to the inverting input port of the amplifier.

2. The capacitive trans-impedance amplifier circuit of claim 1 , wherein the reset switch is a PMOS transistor, the reset signal has a first voltage value during the reset phase, and a second voltage value greater than the first voltage value during the integration phase, the toggling compensation signal of each compensation capacitor is equal to the first compensation voltage value during the reset phase and transitions to the second compensation voltage value a fixed delay after a start of the integration phase, and the first compensation voltage value is greater than the second compensation voltage value.

3. The capacitive trans-impedance amplifier circuit of claim 1 , wherein the reset switch is an NMOS transistor, the reset signal has a first voltage value during the reset phase, and a second voltage value less than the first voltage value during the integration phase, the toggling compensation signal of each compensation capacitor is equal to the first compensation voltage value during the reset phase and transitions to the second compensation voltage value a fixed delay after a start of the integration phase, and the second compensation voltage value is greater than the first compensation voltage value.

4. The capacitive trans-impedance amplifier circuit of claim 1 , wherein at least one of the one or more compensation capacitors is a metal-oxide-metal capacitor including routing metals separated by an oxide material, and having at least one of a lateral finger structure or a vertical structure with two metal layers separated by an oxide layer.

5. The capacitive trans-impedance amplifier circuit of claim 1 , wherein the second port of each compensation capacitor is directly connected to the inverting input port of the amplifier.

6. The capacitive trans-impedance amplifier circuit of claim 1 , wherein at least one of the one or more compensation capacitors is implemented as a metal-oxide-poly capacitor that includes an oxide layer that is used as an isolation layer between a routing metal and a polysilicon layer.

7. The capacitive trans-impedance amplifier circuit of claim 1 , wherein the photodiode is biased to generate a photocurrent upon receiving photons.

8. The capacitive trans-impedance amplifier circuit of claim 1 , wherein a lower voltage value of the first compensation voltage value or the second compensation voltage value is substantially equal to ground.

9. The capacitive trans-impedance amplifier circuit of claim 1 , wherein a greater voltage value of the first compensation voltage value or the second compensation voltage value is substantially equal to a voltage value of a voltage supply of the capacitive trans-impedance amplifier circuit.

10. The capacitive trans-impedance amplifier circuit of claim 1 , wherein the one or more compensation capacitors are a plurality of compensation capacitors configurable to collectively produce a compensation charge deposited at the inverting input port of the amplifier, the compensation charge being controlled by a number of the plurality of compensation capacitors that receive the toggling compensation signal, thereby allowing control of and variation in the compensation charge.

11. The capacitive trans-impedance amplifier circuit of claim 1 , wherein at least one of the first compensation voltage value or the second compensation voltage value is generated by one or more digital-to-analog converters (DACs), and the one or more DACs has an input port configured to receive a digital signal capable of having a plurality of combinations of bit values for allowing control of and variation in a compensation charge deposited at the inverting input port of the amplifier.

12. The capacitive trans-impedance amplifier circuit of claim 11 , wherein at least one of the one or more DACs controls only one of the first compensation voltage value or the second compensation voltage value, and the other compensation voltage value is substantially equal to ground or a voltage value of a voltage supply of the capacitive trans-impedance amplifier circuit.

13. The capacitive trans-impedance amplifier circuit of claim 1 , wherein the toggling compensation signal of at least one of the one or more compensation capacitors is generated using a first DAC configured to output the first compensation voltage value and a second DAC configured to output the second compensation voltage value, and a compensation control signal having substantially same timing as the toggling compensation signal and that controls switching between the output of the first DAC and the output of the second DAC, such that the toggling compensation signal is equal to the first compensation voltage value generated by the first DAC during the reset phase and transitions or switches to the second compensation voltage value generated by the second DAC a fixed delay after a start of the integration phase.

14. The capacitive trans-impedance amplifier circuit of claim 1 , wherein the one or more compensation capacitors are a plurality of binary-scaled compensation capacitors.

15. The capacitive trans-impedance amplifier circuit of claim 1 , wherein a transition time of the reset signal from the reset phase to the integration phase is such that the charge injected by the reset switch at the inverting input port decreases.

16. A pixel array for a CMOS image sensor, the pixel array having a plurality of pixels arranged in a plurality of rows and a plurality of columns, each pixel including a capacitive trans-impedance amplifier circuit, each capacitive trans-impedance amplifier circuit comprising: an amplifier having at least an inverting input port and an output port; a feedback capacitor connected between the inverting input port of the amplifier and the output port of the amplifier; a reset switch, implemented as a MOS transistor having a gate terminal, a source terminal and a drain terminal, the source terminal and the drain terminal being connected between the inverting input port and the output port of the amplifier, and the gate terminal being controlled by a reset signal, wherein the reset switch is configured to be in a closed or active state for establishing a conductive path between the inverting input port of the amplifier and the output port of the amplifier during a reset phase, and configured to be in an open or inactive state during an integration phase; a photodiode directly connected to the inverting input port of the amplifier; and one or more compensation capacitors that are configured to provide a total compensation charge that has an opposite polarity of a charge injected by the reset switch at the inverting input port, each compensation capacitor is not implemented as a gate oxide or a MOS capacitor, and each compensation capacitor having: a first port connected to a compensation signal that is a static signal or a toggling compensation signal that toggles between a first compensation voltage value and a second compensation voltage value, and a second port connected to the inverting input port of the amplifier.

17. The pixel array of claim 16 , wherein the one or more compensation capacitors are a plurality of compensation capacitors, each toggling compensation signal of one of the plurality of compensation capacitors has substantially same timing as toggling compensation signals of other compensation capacitors of the plurality of compensation capacitors, and at least two or more of the plurality of compensation capacitors are binary scaled.

18. The pixel array of claim 16 , wherein the photodiode is implemented on a detector wafer and biased to generate a photocurrent upon receiving photons.

19. A capacitive trans-impedance amplifier circuit with charge injection compensation, comprising: an amplifier having at least an inverting input port and an output port; a feedback capacitor connected between the inverting input port of the amplifier and the output port of the amplifier; a reset switch, implemented as a MOS transistor having a gate terminal, a source terminal and a drain terminal, the source terminal and the drain terminal being connected between the inverting input port and the output port of the amplifier, and the gate terminal being controlled by a reset signal, wherein the reset switch is configured to be in a closed or active state for establishing a conductive path between the inverting input port of the amplifier and the output port of the amplifier during a reset phase, and configured to be in an open or inactive state during an integration phase; and two or more compensation capacitors, wherein at least one of the two or more compensation capacitors compensation capacitor is a metal-oxide-metal capacitor including routing metals separated by an oxide material, and having at least one of a lateral finger structure or a vertical structure with two metal layers separated by an oxide layer, and each compensation capacitor having: a first port connected to a compensation signal that is electrically separate from any other compensation signal connected to a first port of any other compensation capacitor, the compensation signal being a static signal or a toggling compensation signal that toggles between a first compensation voltage value and a second compensation voltage value, and a second port connected to the inverting input port of the amplifier.

20. The capacitive trans-impedance amplifier circuit of claim 19 , wherein each toggling compensation signal of the two or more capacitors has substantially same timing as other compensation capacitors of the two or more capacitors.