Patentable/Patents/US-9484414
US-9484414

Semiconductor device

PublishedNovember 1, 2016
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A MOSFET includes a silicon carbide substrate including a main surface having an off angle with respect to a {0001} plane and a source electrode formed in contact with the main surface. A base surface is exposed at at least a part of a contact interface of the silicon carbide substrate with the source electrode. With such a construction, the MOSFET achieves suppressed variation in threshold voltage.

Patent Claims
4 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A semiconductor device, comprising: a silicon carbide substrate including a main surface having an off angle with respect to a {0001} plane; and an ohmic electrode formed in contact with said main surface, a base surface being exposed at least a part of a contact interface of said silicon carbide substrate with said ohmic electrode, and wherein a length of said base surface in a direction of the off angle is not smaller than 36 nm and not greater than 430 nm.

2

2. The semiconductor device according to claim 1 , wherein said ohmic electrode contains at least one metal of Ni, Ti, and Al.

3

3. The semiconductor device according to claim 2 , wherein said ohmic electrode is composed of a TiAlSi alloy or an NiSi alloy.

4

4. The semiconductor device according to claim 1 , further comprising: an oxide film formed in contact with said silicon carbide substrate; a gate electrode formed in contact with said oxide film such that said oxide film lies between the gate electrode and said silicon carbide substrate; and a drain electrode formed in contact with said silicon carbide substrate, wherein said ohmic electrode is a source electrode, said source electrode and said drain electrode are configured such that a current which flows between said source electrode and said drain electrode can be controlled with a gate voltage applied to said gate electrode, a difference between a first threshold voltage of said semiconductor device which is measured first and a second threshold voltage of said semiconductor device which is measured after application of stress to said semiconductor device continuously for 1000 hours is within ±0.2 V, and application of said stress means application of said gate voltage of −15 V to said gate electrode while a voltage of said source electrode is 0 V and a voltage of said drain electrode is 0 V.

Classification Codes (CPC)

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Patent Metadata

Filing Date

December 19, 2013

Publication Date

November 1, 2016

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Cite as: Patentable. “Semiconductor device” (US-9484414). https://patentable.app/patents/US-9484414

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