Systems and methods for secure delivery of output surface bitmaps to a display engine. An example processing system comprises: an architecturally protected memory; and a processing core communicatively coupled to the architecturally protected memory, the processing core comprising a processing logic configured to implement an architecturally-protected execution environment by performing at least one of: executing instructions residing in the architecturally protected memory and preventing an unauthorized access to the architecturally protected memory; wherein the processing logic is further configured to provide a secure video output path by generating an output surface bitmap encrypted with a first encryption key and storing an encrypted first encryption key in an external memory, wherein the encrypted first encryption key is produced by encrypting the first encryption key with a second encryption key.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A processing system, comprising: an architecturally protected memory; and a hardware processing core, communicatively coupled to the architecturally protected memory, to implement an architecturally-protected execution environment by performing at least one of: executing instructions residing in the architecturally protected memory or preventing an unauthorized access to the architecturally protected memory; wherein the hardware processing core is further to: store, during a reset sequence of the processing system, a key wrapping key in a register of a graphic device; generate, using an application being executed within the architecturally protected execution environment, a surface encryption key; generate an output surface encrypted with the surface encryption key; produce an encrypted surface encryption key by encrypting the surface encryption key using the key wrapping key; bind the surface encryption key to a policy identifying a type of an output interface to be employed for rendering output surfaces encrypted with the surface encryption key; and store the encrypted surface encryption key in an external memory.
2. The processing system of claim 1 , wherein the architecturally protected memory is provided by an enclave page cache (EPC).
3. The processing system of claim 1 , wherein the hardware processing core is to implement a secure enclave.
4. The processing system of claim 1 , wherein the hardware processing core is further to store the output surface in the external memory.
5. The processing system of claim 1 , wherein the graphic device is to decrypt the encrypted surface encryption key, decrypt the output surface using the surface encryption key, and render the output surface.
6. The processing system of claim 1 , wherein the graphic device is provided by a display engine.
7. The processing system of claim 1 , wherein the hardware processing core is further to implement an instruction for encrypting the surface encryption key and binding the surface encryption key to a policy specifying one or more interfaces to be employed for rendering output surfaces encrypted with the surface encryption key.
8. A method, comprising: implementing, by a processing system comprising a hardware processing core communicatively coupled to an architecturally protected memory, an architecturally-protected execution environment by performing at least one of: executing instructions residing in the architecturally protected memory or preventing an unauthorized access to the architecturally protected memory; storing, by the hardware processing core, during a reset sequence of the processing system, a key wrapping key in a register of a graphic device; generating, by an application being executed by the hardware processing core within the architecturally protected execution environment, a surface encryption key; generating, by the hardware processing core, an output surface encrypted with the surface encryption key; producing, by the hardware processing core, an encrypted surface encryption key by encrypting the surface encryption key using the key wrapping key; binding, by the hardware processing core, the surface encryption key to a bit sequence comprising a plurality of bits, wherein each bit of the plurality of bits indicates whether a corresponding output interface type is allowed for rendering output surfaces encrypted with the surface encryption key; and storing, by the hardware processing core, the encrypted surface encryption key in a memory buffer accessible by a graphic device.
9. The method of claim 8 , further comprising: retrieving, by the graphic device, the key wrapping key; decrypting, using the key wrapping key, the encrypted surface encryption key; decrypting the output surface using the surface encryption key; and rendering the output surface.
10. The method of claim 8 , wherein the graphic device is provided by a display engine.
11. The method of claim 8 , wherein the architecturally protected execution environment is provided by a secure enclave.
12. The method of claim 8 , wherein the architecturally protected execution environment comprises a protected memory.
13. The method of claim 8 , wherein the surface encryption key is generated using a random number generator.
14. The method of claim 8 , further comprising implementing a replay protection by applying a key derivation function to a random number and a surface counter to generate the surface encryption key.
15. A computer-readable non-transitory storage medium comprising executable instructions that, when executed by a processing system comprising a hardware processing core communicatively coupled to an architecturally protected memory, cause the processing system to perform operations, comprising: implementing an architecturally-protected execution environment by performing at least one of: executing instructions residing in the architecturally protected memory or preventing an unauthorized access to the architecturally protected memory; storing, during a reset sequence of the processing system, a key wrapping key in a register of a graphic device; generating, by an application being executed within the architecturally protected execution environment, a surface encryption key; generating an output surface encrypted with the surface encryption key; producing an encrypted surface encryption key by encrypting the surface encryption key using the key wrapping key; binding the surface encryption key to a bit sequence comprising a plurality of bits, wherein each bit of the plurality of bits indicates whether a corresponding output interface type is allowed for rendering output surfaces encrypted with the surface encryption key; and storing the encrypted surface encryption key in a memory buffer accessible by a graphic device.
16. The computer-readable non-transitory storage medium of claim 15 , further comprising executable instructions causing the processing system to perform operations, comprising: retrieving, by the graphic device, the key wrapping key; decrypting, using the key wrapping key, the encrypted surface encryption key; decrypting the output surface using the surface encryption key; and rendering the output surface.
17. The computer-readable non-transitory storage medium of claim 15 , wherein the architecturally protected execution environment is provided by a secure enclave.
18. The computer-readable non-transitory storage medium of claim 15 , wherein producing the encrypted surface encryption key comprises binding the surface encryption key to a policy specifying one or more interfaces to be employed for rendering output surfaces encrypted with the surface encryption key.
19. The computer-readable non-transitory storage medium of claim 15 , further comprising executable instructions the processing system to implement a replay protection by applying a key derivation function to a random number and a surface counter to generate the surface encryption key.
20. The system of claim 1 , wherein the hardware processing core is further to: bind the surface encryption key to a policy identifying a target device to be employed for rendering output surfaces encrypted with the surface encryption key.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 25, 2013
November 22, 2016
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