A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming a semiconductor structure comprising: etching a shallow trench laterally surrounding a stack of a top semiconductor portion, a buried insulator portion, and an upper portion of a handle substrate in a semiconductor-on-insulator (SOI) substrate; depositing a stack of a dielectric metal oxide liner and a silicon nitride liner in said shallow trench; filling said shallow trench with a shallow trench fill portion; recessing said dielectric metal oxide liner to a depth below the horizontal plane of a bottom surface of said top semiconductor portion, wherein a divot laterally surrounding said top semiconductor portion is formed by said recessing; depositing a contact-level dielectric layer over said top semiconductor portion and said shallow trench fill portion; etching a contact via hole through said contact-level dielectric layer and a portion of said shallow trench fill portion employing at least one of said dielectric metal oxide liner and said silicon nitride liner as a stopping layer; and forming a contact via structure by depositing a conductive material within said contact via hole, wherein a portion of said contact via structure is formed directly on a vertical sidewall surface of said top semiconductor portion.
2. The method of claim 1 , wherein a portion of said contact via structure is in direct contact with a topmost horizontal surface of said dielectric metal oxide liner and a topmost surface of said silicon nitride liner.
3. The method of claim 1 , wherein said dielectric metal oxide liner is recessed to a depth between a top surface of said buried insulator portion and a bottom surface of said buried insulator portion.
4. The method of claim 3 , wherein another portion of said contact via structure is formed directly on a vertical sidewall surface of said buried insulator portion.
5. The method of claim 1 , further comprising recessing said silicon nitride liner to a depth below the horizontal plane of a bottom surface of said top semiconductor portion.
6. The method of claim 5 , wherein said silicon nitride liner is recessed to a depth below the horizontal plane of a bottom surface of said buried insulator portion.
7. The method of claim 6 , wherein said contact via structure is in direct contact with a vertical sidewall of said dielectric metal oxide liner and a topmost surface of said silicon nitride liner.
8. The method of claim 7 , wherein a portion of said contact via structure is in direct contact with a vertical sidewall surface of said shallow trench fill portion.
9. The method of claim 8 , wherein said shallow trench fill portion located within said shallow trench contacts said silicon nitride liner.
10. The method of claim 1 , further comprising forming a contact-level nitride layer on said shallow trench fill portion.
11. The method of claim 10 , wherein said contact-level nitride layer is in direct contact with a topmost surface of said shallow trench fill portion and a bottommost surface of said contact-level dielectric layer.
12. The method of claim 1 , wherein said stack of said dielectric metal oxide liner and said silicon nitride liner are deposited as contiguous layers above a topmost surface of said stack of said top semiconductor portion, said buried insulator portion, and said upper portion of a handle substrate in a semiconductor-on-insulator (SOI) substrate.
13. The method of claim 12 , further comprising: removing said stack of said dielectric metal oxide liner and said silicon nitride liner from above said top semiconductor portion; and forming a gate stack including a gate dielectric after said removal of said stack from above said top semiconductor portion.
14. The method of claim 13 , further comprising forming a gate spacer on said gate stack.
15. The method of claim 1 , further comprising forming a raised source region and a raised drain region on said top semiconductor portion.
16. The method of claim 15 , wherein said raised source region and said raised drain region comprise a doped semiconductor material.
17. The method of claim 1 , wherein said dielectric metal oxide liner comprises a nitrogen, carbon, fluorine or chlorine.
18. The method of claim 1 , wherein a topmost surface of said shallow trench fill portion is located above a topmost surface of said top semiconductor portion.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 17, 2015
November 22, 2016
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