Embodiments of the invention include a method for forming a FinFET device and the resulting structure. A semiconductor device including a substrate, a silicon-germanium fin formed on the substrate, a dummy gate formed on the fin, and a first set of spacers formed on the exposed sidewalls of the dummy gate is provided. Xenon is implanted into the exposed portions of the fin. A second set of spacers are formed on the exposed sidewalls of the first set of spacer. A dopant is implanted into the exposed portions of the fin. The semiconductor device is thermally annealed, such that the dopants diffuse into the adjacent portions of the fin. The dummy gate is replaced with a gate structure.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device, the semiconductor device comprising: an NFET device and a PFET device separated by an isolation layer, wherein the NFET device and the PFET device each comprise: a substrate; a fin formed on the substrate, wherein the fin comprises silicon-germanium; a gate structure formed on the fin; a set of spacers formed laterally on sidewalls of the gate structure; and a source/drain region formed laterally on the fin and adjacent to each spacer of the set of spacers; an annealed region, containing implanted xenon, located at least partially beneath the spacer of the NFET device, wherein an edge of the annealed region is aligned with an edge of a spacer of the set of spacers; a doped region located at least partially beneath the spacer of the PFET device; and wherein the NFET device has a larger physical gate length than the PFET device, and an effective gate length of the NFET device and an effective gate length of the PFET device are equal.
2. The semiconductor device of claim 1 , wherein the gate structure comprises a metal gate and a high-k gate dielectric layer.
3. The semiconductor device of claim 1 , wherein the physical gate length is the distance between the interior of the spacers.
4. The semiconductor device of claim 1 , wherein the physical gate length is the width of the gate structure.
5. The semiconductor device of claim 1 , wherein the effective gate length of the NFET device is the distance between each of the annealed regions; and wherein the effective gate length of the PFET device is the distance between each of the doped regions.
6. The semiconductor device of claim 1 , wherein the fin has a composition of at least 25 percent germanium.
7. The semiconductor device of claim 1 , further comprising: an interlayer dielectric formed on exposed portions of the substrate and the source/drain region.
8. The semiconductor device of claim 1 , wherein the substrate includes a buried oxide layer (BOX).
9. The semiconductor device of claim 1 , further comprising a metal contact formed in the gate.
10. The semiconductor device of claim 1 , further comprising a metal contact formed in the source/drain region.
11. The semiconductor device of claim 1 , wherein the substrate is of a different material composition than the fin formed on the substrate.
12. The semiconductor device of claim 1 , wherein the semiconductor device is a FinFET device.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 25, 2015
December 6, 2016
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