A semiconductor package is provided. In one configuration, the semiconductor package includes a substrate. A conductive trace is disposed on the substrate. A conductive pillar bump is disposed on the conductive trace, wherein the conductive bump is coupled to a die. In another configuration, a first conductive trace is disposed on the substrate, and a second conductive trace is disposed on the substrate. In the second configuration, a conductive pillar bump disposed on the second conductive trace, connecting to a conductive bump or a metal pad of the semiconductor die. A first conductive structure is disposed between the second conductive trace and the conductive pillar bump or between the second conductive trace and the substrate, and a die is disposed over the first conductive trace.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor package, comprising: a substrate; a conductive trace disposed on the substrate; a conductive pillar bump disposed on the conductive trace, wherein the conductive pillar bump is coupled to a die; and a solder resistance layer disposed on the substrate, wherein an extending portion of the solder resistance layer extends along the conductive trace into an overlapping region between the die and the substrate.
2. The semiconductor package as claimed in claim 1 , wherein the conductive trace comprises a first portion having a first width and a second portion having a second width, and the conductive pillar bump is disposed on the second portion of the conductive trace.
3. The semiconductor package as claimed in claim 2 , wherein the semiconductor package comprises a plurality of conductive pillar bumps disposed on the second portion of the conductive trace.
4. The semiconductor package as claimed in claim 1 , wherein the semiconductor package further comprises a metal pad located between the conductive trace and the substrate.
5. The semiconductor package as claimed in claim 1 , wherein the semiconductor package further comprises a metal pad located between the conductive pillar bump and the conductive trace.
6. The semiconductor package as claimed in claim 1 , wherein the conductive trace comprises a plurality of conductive layers and a metal pad, wherein the metal pad is sandwiched by the plurality of conductive layers.
7. The semiconductor package as claimed in claim 1 , wherein the extending portion of the solder resistance layer covers a portion of the conductive trace, and a width of the extending portion of the solder resistance layer is larger than that of the portion of the conductive trace.
8. The semiconductor package as claimed in claim 1 , wherein the extending portion of the solder resistance layer covers a portion of the conductive trace, and the extending portion of the solder resistance layer and the portion of the conductive trace collectively have a T-shaped cross section.
9. The semiconductor package as claimed in claim 1 , wherein the solder resistance layer further has a second extending portion, and the conductive pillar bump is positioned between the extending portion and the second extending portion.
10. The semiconductor package as claimed in claim 1 , wherein the extending portion is separated from the substrate.
11. The semiconductor package as claimed in claim 1 , further comprising an underfill material between the substrate and the die, wherein a portion of the underfill material is sandwiched by the extending portion and the die.
12. The semiconductor package as claimed in claim 1 , further comprising an underfill material between the substrate and the die, wherein a portion of the underfill material is sandwiched by the extending portion and the substrate.
13. The semiconductor package as claimed in claim 1 , further comprising an underfill material between the substrate and the die, wherein a portion of the underfill material is in direct contact with the substrate.
14. A semiconductor package, comprising: a substrate; a conductive trace disposed on the substrate; a conductive pillar bump disposed on the conductive trace, wherein the conductive pillar bump is coupled to a die; and a solder resistance layer, wherein a portion of the solder resistance layer and a portion of the conductive trace collectively have a T-shaped cross section, wherein the portion of the solder resistance layer forms a top, horizontal portion of the T-shape, and the portion of the first conductive trace forms a lower, vertical portion of the T-shape that contacts the top, horizontal portion at a substantial midpoint of the top horizontal portion.
15. The semiconductor package as claimed in claim 14 , wherein a width of the portion of the solder resistance layer is larger than that of the portion of the conductive trace.
16. The semiconductor package as claimed in claim 14 , wherein the portion of the solder resistance layer is separated from the substrate.
17. The semiconductor package as claimed in claim 14 , further comprising an underfill material between the substrate and the die, wherein a portion of the underfill material is in direct contact with the substrate.
18. The semiconductor package as claimed in claim 14 , further comprising an underfill material between the substrate and the die, wherein the portion of the solder resistance layer is embedded in the underfill material.
19. The semiconductor package as claimed in claim 14 , wherein a bottom surface of the portion of the solder resistance layer faces the conductive trace, and a portion of the bottom surface is exposed from the portion of the conductive trace.
20. The semiconductor package as claimed in claim 19 , further comprising an underfill material between the substrate and the die, wherein the portion of the bottom surface is wrapped by the underfill material.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 2, 2015
December 13, 2016
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