Apparatuses and methods concerning regulation of load currents are disclosed. As an example, one apparatus includes a first clock generation circuit configured to generate a first clock signal with a frequency spectrum having a first frequency range. A second clock generation circuit is configured to produce a second clock signal by spreading the frequency spectrum of the first clock signal to have a second frequency range that is wider than the first frequency range. The second clock signal has a frequency spectrum extending outside of the frequency range. The apparatus includes a third circuit configured to regulate a voltage at a supply node as a function of the second clock signal. A current regulation circuit is configured to regulate current in a circuit path, from the supply node and passing through a load circuit coupled to the current regulator, as a function of the first clock signal.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus comprising: a first circuit configured and arranged to generate a first clock signal with a frequency spectrum having a first frequency range; a second circuit coupled to the first circuit and configured and arranged to generate a second clock signal from the first clock signal by spreading the frequency spectrum of the first clock to have a second frequency range that is wider than the first frequency range; a third circuit configured and arranged to provide a regulated voltage at a supply node by coupling a power source to the supply node in a first mode of operation, uncoupling the power source from the supply node in a second mode of operation, and switching between the first and second modes of operation at a plurality of frequencies derived from the frequency spectrum of the second clock signal; and a fourth circuit configured and arranged to regulate current in a circuit path, from the supply node and passing through a load circuit coupled to the current regulator, according to the first clock signal.
2. The apparatus of claim 1 , wherein the second circuit includes a current source configured and arranged to provide a current having pseudorandom variation a capacitor configured and arranged to receive the current from the current source, a comparator configured and arranged to compare a voltage stored by the capacitor to a reference voltage; and a switching circuit configured and arranged to discharge the capacitor in response to the comparator indicating that the stored voltage exceeds the reference voltage.
3. The apparatus of claim 2 , wherein the current source includes a pseudorandom noise generator configured and arranged to generate an M-bit pseudorandom number; a first current source configured and arranged to provide a constant current to the capacitor; and M current sources, each coupled to receive a respective bit of the M-bit pseudorandom number and configured and arranged to provide a respective current to the capacitor in response to the respective bit having a first value.
4. The apparatus of claim 2 , wherein the switching circuit is configured and arranged to synchronize discharging of the capacitor, in response to the comparator indicating that the stored voltage exceeds the reference voltage, with an edge of the first clock signal.
5. The apparatus of claim 2 , wherein the second circuit is configured and arranged to provide a signal output by the comparator as the second clock signal.
6. The apparatus of claim 1 , wherein the third circuit includes a boost converter.
7. The apparatus of claim 1 , wherein the fourth circuit includes a pulse generation circuit configured and arranged to generate a pulsed signal as a function of the first clock signal; and a pulse controlled current source configured and arranged to regulate the current in the circuit path according to the pulsed signal.
8. The apparatus of claim 7 , wherein the fourth circuit further includes a second pulse controlled current source configured and arranged to regulate current in a second circuit path, from the supply node and passing through a second load circuit coupled to the fourth circuit, according to the pulsed signal.
9. The apparatus of claim 8 , wherein the pulse generation circuit is configured and arranged to adjust currents in the respective circuit paths by adjusting a duty cycle of the pulsed signal.
10. The apparatus of claim 1 , further comprising the load circuit; and wherein the load circuit includes a plurality of light emitting diodes coupled in series along the circuit path through the load circuit.
11. A method, comprising: generating a first clock signal with a frequency spectrum having a first frequency range; generating a second clock signal by spreading frequency spectrum of the first clock signal to have a second frequency range that is wider than the first frequency range; providing a regulated voltage at a supply node as a function of the second clock signal; and regulating current in a circuit path, from the supply node and passing through a load circuit, as a function of the first clock signal.
12. The method of claim 11 , wherein the spreading of the frequency spectrum of the first clock signal includes generating a current having pseudorandom variation; charging a capacitor by providing the current to the capacitor; comparing a voltage stored by the capacitor to a reference voltage; and discharging the capacitor in response to the voltage stored by the capacitor exceeding the reference voltage.
13. The method of claim 12 , further comprising dividing the first clock signal to produce an intermediary clock signal.
14. The method of claim 13 , further comprising synchronizing the discharging of the capacitor to an edge of the first clock signal.
15. The method of claim 12 , further comprising: setting the second clock signal to a first value in response to the voltage stored by the capacitor exceeding the reference voltage; and setting the second clock signal to a second value in response to the reference voltage exceeding the voltage stored by the capacitor.
16. The method of claim 11 , wherein the generating of the current having pseudorandom variation includes: generating an M-bit pseudorandom number; and for each bit of the M-bit pseudorandom number, enabling a respective current source in response to the bit being set to a first value and disabling the respective current source in response to the bit being set to a second value.
17. The method of claim 11 , wherein the generating of the current is performed using a boost converter clocked by the second clock signal.
18. The method of claim 11 , wherein the regulating of current in the circuit path includes generating a pulse width modulated waveform from the first clock signal; and providing the pulse width modulated waveform to a pulse width controlled current source.
19. The method of claim 18 , further comprising wherein the regulating of current in the circuit path includes generating a pulse width modulated waveform from the first clock signal; and providing the pulse width modulated waveform to a pulse width controlled current source.
20. The method of claim 11 , further comprising regulating current in a second circuit path, from the supply node and passing through a second load circuit, as a function of the first clock signal.
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June 29, 2015
December 20, 2016
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