Method and devices for time and frequency synchronization using a phase locked loop

1. A slave device connected to a master device having a master clock over a network, wherein the slave device includes: a slave clock; and a digital phase locked loop including a phase detector, a loop filter, a phase accumulator and a counter, wherein: the slave device is arranged to: exchange with the master device, timing messages and to record timestamps which are: the time of sending of said timing messages from the master device according to the master clock; the time of receipt of said timing messages according to the slave clock; the time of sending of said timing messages according to the slave clock; and the time of receipt of said timing messages according to the master clock, estimate the skew and offset of the slave clock relative to the master clock from said timestamps; and synchronize said slave clock to the master clock based on the estimated skew and offset to produce a master time estimate; the digital phase locked loop processes the master time estimate as follows: on receipt of a first estimate of the master time, the counter is initialised; on receipt of subsequent estimates of the master time, the phase detector is arranged to detect a phase difference between the output of the counter and the received estimate and produce an error signal representing that difference; the error signal is filtered by the loop filter to produce a filtered error signal; the filtered error signal is used to control the frequency of the phase accumulator; and the output of the phase accumulator increments the counter and also provides a clock frequency of the slave clock which is synchronized to the frequency of the master clock; and wherein the slave device uses the output of the counter as the clock time of the slave clock which is synchronized to the time of the master clock.

2. The slave device according to claim 1 further comprising a direct digital synthesizer producing an analog frequency signal from the output of the phase accumulator, the direct digital synthesizer including: the phase accumulator; an oscillator; a mapping device; and a digital-to-analog converter.

3. The slave device according to claim 2 further comprising a low-pass filter arranged to filter the output of the direct digital synthesizer.

4. The slave device according to claim 1 wherein the counter of the digital phase locked loop is also used to provide timestamps for the time of receipt and of sending of timing messages at/from the slave device.

5. The slave device according to claim 4 wherein the counter is initialized on receipt by the slave device of the first timing message from the master device, and the counter is reset on receipt of the first master time estimate to said first master time estimate.

6. The slave device according to claim 1 further comprising a second free-running counter, wherein the second counter is used to provide timestamps for the time of receipt and sending of timing messages at/from the slave device.

7. The slave device according to claim 1 , wherein the slave device is arranged to estimate the skew and offset of the slave clock relative to the master clock by applying an exponentially weighted recursive least squares algorithm to a state-space formulation of the frequency and time of the slave clock and the timestamps.

9. The slave device according to claim 8 , wherein the forgetting factor λ n is dynamic.

10. A method of synchronizing the time and frequency of a slave clock in a slave device to a master clock in a master device which is connected to the slave device over a network, the method including the steps of: exchanging, between the master device and the slave device, timing messages and timestamps which are: the time of sending of timing messages from the master device according to the master clock; the time of receipt of said timing messages according to the slave clock; the time of sending of said timing messages according to the slave clock; and the time of receipt of said timing messages according to the master clock, estimating the skew and offset of the slave clock relative to the master clock from said timestamps; and synchronizing said slave clock to the master clock based on the estimated skew and offset to produce a master time estimate; using a digital phase locked loop including a phase detector, a loop filter, a phase accumulator and a counter, processing the master time estimate as follows: on receipt of a first estimate of the master time, initializing the counter; on receipt of subsequent estimates of the master time, detecting, using the phase detector, a phase difference between the output of the counter and the received estimate and producing an error signal representing that difference; filtering the error signal using the loop filter to produce a filtered error signal; controlling the frequency of the phase accumulator using the filtered error signal; and incrementing counter using the output of the phase accumulator, and obtaining a clock frequency of the slave clock which is synchronized to the frequency of the master clock as the output of the phase accumulator; and wherein the output of the counter as the clock time of the slave clock which is synchronized to the time of the master clock.

11. The method according to claim 10 further including the step of producing an analog frequency signal from the output of the phase accumulator using a direct digital synthesizer including the steps of: mapping the output of the phase accumulator to produce a digital waveform; and converting said digital waveform to an analog waveform using a digital-to-analog converter.

12. The method according to claim 11 further including the step of low-pass filtering the analog waveform to produce a smoothed waveform.

13. The method according to claim 10 wherein the timestamps for the time of receipt and of sending of timing messages at/from the slave device are provided by the counter of the digital phase locked loop.

14. The method according to claim 13 further including the steps of: initializing the counter on receipt by the slave device of the first timing message from the master device, and resetting the counter to said first master time estimate on receipt of the first master time estimate.

15. The method according to claim 10 wherein the timestamps for the time of receipt and sending of timing messages at/from the slave device are provided by a second free-running counter.

16. The method according to claim 10 , wherein the step of estimating the offset and skew of the slave clock compared to the master clock applies an exponentially weighted recursive least squares algorithm to a state-space formulation of the frequency and time of the slave clock and the timestamps.

18. The method according to claim 17 , wherein the forgetting factor λ n is dynamic.

19. A time and frequency synchronisation system for a network, the system including: a master device having a master clock; a slave device having a slave clock; and a network connecting the master and slave devices, wherein: the slave clock comprises: a slave clock; and a digital phase locked loop including a phase detector, a loop filter, a phase accumulator and a counter, wherein: the slave device is arranged to: exchange with the master device, timing messages and to record timestamps which are: the time of sending of said timing messages from the master device according to the master clock; the time of receipt of said timing messages according to the slave clock; the time of sending of said timing messages according to the slave clock; and the time of receipt of said timing messages according to the master clock, estimate the skew and offset of the slave clock relative to the master clock from said timestamps; and synchronize said slave clock to the master clock based on the estimated skew and offset to produce a master time estimate; the digital phase locked loop processes the master time estimate as follows: on receipt of a first estimate of the master time, the counter is initialised; on receipt of subsequent estimates of the master time, the phase detector is arranged to detect a phase difference between the output of the counter and the received estimate and produce an error signal representing that difference; the error signal is filtered by the loop filter to produce a filtered error signal; the filtered error signal is used to control the frequency of the phase accumulator; and the output of the phase accumulator increments the counter and also provides a clock frequency of the slave clock which is synchronized to the frequency of the master clock; and wherein the slave device uses the output of the counter as the clock time of the slave clock which is synchronized to the time of the master clock.

20. The system according to claim 19 wherein the slave device further comprises a direct digital synthesizer producing an analog frequency signal from the output of the phase accumulator, the direct digital synthesizer including: the phase accumulator; an oscillator; a mapping device; and a digital-to-analog converter.

21. The system according to claim 20 wherein the slave device further comprises a low-pass filter arranged to filter the output of the direct digital synthesizer.

22. The system according to claim 19 wherein the counter of the digital phase locked loop is also used to provide timestamps for the time of receipt and of sending of timing messages at/from the slave device.

23. The system according to claim 22 wherein the counter is initialized on receipt by the slave device of the first timing message from the master device, and the counter is reset on receipt of the first master time estimate to said first master time estimate.

24. The system according to claim 19 wherein the slave device further comprises a second free-running counter, wherein the second counter is used to provide timestamps for the time of receipt and sending of timing messages at/from the slave device.

25. The time and frequency synchronisation system according to claim 19 , wherein the slave device is arranged to estimate the skew and offset of the slave clock relative to the master clock by applying an exponentially weighted recursive least squares algorithm to a state-space formulation of the frequency and time of the slave clock and the timestamps.

27. The system according to claim 26 , wherein the forgetting factor λ n is dynamic.